Subrata Banik has uploaded this change for review.

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mb/{google,intel,siemens}/devicetree.cb: Enable CSE device

Enable CSE PCI device Bus 0: Device 0x0f: Function 0x00 to let
Intel common cse block code can use this device.

Calling me_read_config32(offset) function from ramstage:

Without this CL:
HECI: Global Reset(Type:1) Command
BUG: me_read_config32 requests hidden 00:0f.0
PCI: dev is NULL!

With this CL:
HECI: Global Reset(Type:1) Command
HECI: Global Reset success!

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I97d221ae52b4b03ecd859d708847ad77fe4bf465
---
M src/mainboard/google/reef/variants/baseboard/devicetree.cb
M src/mainboard/google/reef/variants/coral/devicetree.cb
M src/mainboard/google/reef/variants/pyro/devicetree.cb
M src/mainboard/google/reef/variants/sand/devicetree.cb
M src/mainboard/google/reef/variants/snappy/devicetree.cb
M src/mainboard/intel/apollolake_rvp/devicetree.cb
M src/mainboard/intel/leafhill/devicetree.cb
M src/mainboard/intel/minnow3/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
14 files changed, 14 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/45469/1
diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
index 4c35bd2..4c93096 100644
--- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
@@ -139,6 +139,7 @@
device generic 0 on end
end
end
+ device pci 0f.0 on end # - CSE
device pci 11.0 off end # - ISH
device pci 12.0 off end # - SATA
device pci 13.0 off end # - Root Port 2 - PCIe-A 0
diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb
index f987e1d..249e2c8 100644
--- a/src/mainboard/google/reef/variants/coral/devicetree.cb
+++ b/src/mainboard/google/reef/variants/coral/devicetree.cb
@@ -139,6 +139,7 @@
device generic 0 on end
end
end
+ device pci 0f.0 on end # - CSE
device pci 11.0 off end # - ISH
device pci 12.0 off end # - SATA
device pci 13.0 off end # - Root Port 2 - PCIe-A 0
diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb
index 1282edb..9ed1c4c 100644
--- a/src/mainboard/google/reef/variants/pyro/devicetree.cb
+++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb
@@ -148,6 +148,7 @@
device generic 0 on end
end
end
+ device pci 0f.0 on end # - CSE
device pci 11.0 off end # - ISH
device pci 12.0 off end # - SATA
device pci 13.0 off end # - Root Port 2 - PCIe-A 0
diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb
index ad76a91..0b1134c 100644
--- a/src/mainboard/google/reef/variants/sand/devicetree.cb
+++ b/src/mainboard/google/reef/variants/sand/devicetree.cb
@@ -135,6 +135,7 @@
device generic 0 on end
end
end
+ device pci 0f.0 on end # - CSE
device pci 11.0 off end # - ISH
device pci 12.0 off end # - SATA
device pci 13.0 off end # - Root Port 2 - PCIe-A 0
diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb
index a82400f..fdd84dd 100644
--- a/src/mainboard/google/reef/variants/snappy/devicetree.cb
+++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb
@@ -144,6 +144,7 @@
device generic 0 on end
end
end
+ device pci 0f.0 on end # - CSE
device pci 11.0 off end # - ISH
device pci 12.0 off end # - SATA
device pci 13.0 off end # - Root Port 2 - PCIe-A 0
diff --git a/src/mainboard/intel/apollolake_rvp/devicetree.cb b/src/mainboard/intel/apollolake_rvp/devicetree.cb
index f7e82a0..dd12a5b 100644
--- a/src/mainboard/intel/apollolake_rvp/devicetree.cb
+++ b/src/mainboard/intel/apollolake_rvp/devicetree.cb
@@ -22,6 +22,7 @@
device pci 0d.2 on end # - SPI
device pci 0d.3 on end # - Shared SRAM
device pci 0e.0 on end # - Audio
+ device pci 0f.0 on end # - CSE
device pci 11.0 on end # - ISH
device pci 12.0 on end # - SATA
device pci 13.0 on end # - PCIe-A 0
diff --git a/src/mainboard/intel/leafhill/devicetree.cb b/src/mainboard/intel/leafhill/devicetree.cb
index 6c872b1..e2f2f8e 100644
--- a/src/mainboard/intel/leafhill/devicetree.cb
+++ b/src/mainboard/intel/leafhill/devicetree.cb
@@ -22,6 +22,7 @@
device pci 0d.2 on end # - SPI
device pci 0d.3 on end # - Shared SRAM
device pci 0e.0 on end # - Audio
+ device pci 0f.0 on end # - CSE
device pci 11.0 on end # - ISH
device pci 12.0 on end # - SATA
device pci 13.0 on end # - PCIe-A 0
diff --git a/src/mainboard/intel/minnow3/devicetree.cb b/src/mainboard/intel/minnow3/devicetree.cb
index 6c872b1..e2f2f8e 100644
--- a/src/mainboard/intel/minnow3/devicetree.cb
+++ b/src/mainboard/intel/minnow3/devicetree.cb
@@ -22,6 +22,7 @@
device pci 0d.2 on end # - SPI
device pci 0d.3 on end # - Shared SRAM
device pci 0e.0 on end # - Audio
+ device pci 0f.0 on end # - CSE
device pci 11.0 on end # - ISH
device pci 12.0 on end # - SATA
device pci 13.0 on end # - PCIe-A 0
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
index 0e72fcf..c927dcc 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
@@ -69,6 +69,7 @@
device pci 0d.2 on end # - SPI
device pci 0d.3 off end # - Shared SRAM
device pci 0e.0 on end # - Audio
+ device pci 0f.0 on end # - CSE
device pci 11.0 on end # - ISH
device pci 12.0 on end # - SATA
device pci 13.0 on end # - RP 2 - PCIe A 0 - MACPHY
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
index bee531f..8887929 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
@@ -61,6 +61,7 @@
device pci 0d.2 on end # - SPI
device pci 0d.3 off end # - Shared SRAM
device pci 0e.0 on end # - Audio
+ device pci 0f.0 on end # - CSE
device pci 11.0 on end # - ISH
device pci 12.0 on end # - SATA
device pci 13.0 on end # - RP 2 - PCIe A 0
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
index e1e79b4..9747292 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
@@ -57,6 +57,7 @@
device pci 0d.2 on end # - SPI
device pci 0d.3 off end # - Shared SRAM
device pci 0e.0 on end # - Audio
+ device pci 0f.0 on end # - CSE
device pci 11.0 on end # - ISH
device pci 12.0 on end # - SATA
device pci 13.0 on end # - RP 2 - PCIe A 0
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
index be50408..89fa45e9 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
@@ -58,6 +58,7 @@
device pci 0d.2 on end # - SPI
device pci 0d.3 off end # - Shared SRAM
device pci 0e.0 on end # - Audio
+ device pci 0f.0 on end # - CSE
device pci 11.0 on end # - ISH
device pci 12.0 on end # - SATA
device pci 13.0 on end # - RP 2 - PCIe A 0
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
index 33664fe..05ec8b4 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
@@ -60,6 +60,7 @@
device pci 0d.2 on end # - SPI
device pci 0d.3 off end # - Shared SRAM
device pci 0e.0 on end # - Audio
+ device pci 0f.0 on end # - CSE
device pci 11.0 on end # - ISH
device pci 12.0 on end # - SATA
device pci 13.0 on end # - RP 2 - PCIe A 0
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
index a865f9f..4b0367f 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
@@ -28,6 +28,7 @@
device pci 0d.2 on end # - SPI
device pci 0d.3 off end # - Shared SRAM
device pci 0e.0 on end # - Audio
+ device pci 0f.0 on end # - CSE
device pci 11.0 on end # - ISH
device pci 12.0 on end # - SATA
device pci 13.0 on end # - RP 2 - PCIe A 0

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I97d221ae52b4b03ecd859d708847ad77fe4bf465
Gerrit-Change-Number: 45469
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik@intel.com>
Gerrit-MessageType: newchange