[coreboot-gerrit] Change in coreboot[master]: soc/amd/picasso: Cache ramstage load

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37492 )

Change subject: soc/amd/picasso: Cache ramstage load
......................................................................

soc/amd/picasso: Cache ramstage load

Set a variable MTRR to WB for the region where ramstage will be loaded.
Only a single one is required now that SMM memory is in cbmem.

Change-Id: I0a31802052ac7b20871f41c80d0416ee09f8f87c
Signed-off-by: Marshall Dawson 
---
M src/soc/amd/picasso/include/soc/cpu.h
M src/soc/amd/picasso/romstage.c
2 files changed, 22 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/37492/1

diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h
index 9af4c0c..338e871 100644
--- a/src/soc/amd/picasso/include/soc/cpu.h
+++ b/src/soc/amd/picasso/include/soc/cpu.h
@@ -18,9 +18,6 @@

#include <device/device.h>

-#define SOC_EARLY_VMTRR_FLASH 1
-#define SOC_EARLY_VMTRR_TEMPRAM 2
-
 #define CSTATE_BASE_REG 0xc0010073

void picasso_init_cpus(struct device *dev);
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c
index 22b717d..f2e3375 100644
--- a/src/soc/amd/picasso/romstage.c
+++ b/src/soc/amd/picasso/romstage.c
@@ -16,6 +16,7 @@
 #include <arch/acpi.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
 #include <cpu/amd/mtrr.h>
 #include <arch/exception.h>
 #include <delay.h>
@@ -34,6 +35,25 @@
    /* By default, don't do anything */
 }

+static void set_mtrrs_for_ramstage(void)
+{
+	uintptr_t mem_top;
+	int mtrr;
+
+	mem_top = (uintptr_t)cbmem_top();
+
+	/* Cache anticipated ramstage location through the top of cbmem.
+	 * Unlike some other implementations, TSEG is in cbmem so it will
+	 * be cached as well.
+	 */
+	mtrr = get_free_var_mtrr();
+	if (mtrr < 0) {
+		printk(BIOS_WARNING, "Warning: Unable to make ramstage cacheable\n");
+		return;
+	}
+	set_var_mtrr(mtrr, mem_top - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK);
+}
+
 static void soc_romstage(uint32_t bist)
 {
    uintptr_t top_of_mem;
@@ -68,6 +88,8 @@
    	printk(BIOS_ERR, "Failed to set romstage handoff data\n");

post_code(0x45);
+	set_mtrrs_for_ramstage();
+	post_code(0x46);
    run_ramstage();

post_code(0x50); /* Should never see this post code. */