Attention is currently required from: Patrick Rudolph.
Kyösti Mälkki has uploaded this change for review.
sb,soc/intel: Refactor power_on_after_fail option
It's only necessary to call get_option() with SLP_TYP S5.
Change-Id: Ic821b429a58a2c0713ec338904364ec57bfbcfce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
---
M src/soc/intel/broadwell/pch/smihandler.c
M src/southbridge/intel/common/smihandler.c
M src/southbridge/intel/lynxpoint/smihandler.c
3 files changed, 40 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/49251/1
diff --git a/src/soc/intel/broadwell/pch/smihandler.c b/src/soc/intel/broadwell/pch/smihandler.c
index c6632da..3a54749 100644
--- a/src/soc/intel/broadwell/pch/smihandler.c
+++ b/src/soc/intel/broadwell/pch/smihandler.c
@@ -125,13 +125,9 @@
printk(BIOS_INFO, "Backlight turned off\n");
}
-static void southbridge_smi_sleep(void)
+static int power_on_after_fail(void)
{
- u8 reg8;
- u32 reg32;
- u8 slp_typ;
u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
- u16 pmbase = get_pmbase();
/* save and recover RTC port values */
u8 tmp70, tmp72;
@@ -140,6 +136,15 @@
get_option(&s5pwr, "power_on_after_fail");
outb(tmp70, 0x70);
outb(tmp72, 0x72);
+ return (s5pwr == MAINBOARD_POWER_ON);
+}
+
+static void southbridge_smi_sleep(void)
+{
+ u8 reg8;
+ u32 reg32;
+ u8 slp_typ;
+ u16 pmbase = get_pmbase();
/* First, disable further SMIs */
disable_smi(SLP_SMI_EN);
@@ -193,12 +198,10 @@
/* Always set the flag in case CMOS was changed on runtime. For
* "KEEP", switch to "OFF" - KEEP is software emulated
*/
- reg8 = pci_read_config8(PCH_DEV_LPC, GEN_PMCON_3);
- if (s5pwr == MAINBOARD_POWER_ON)
- reg8 &= ~1;
+ if (power_on_after_fail())
+ pci_and_config8(PCH_DEV_LPC, GEN_PMCON_3, ~1);
else
- reg8 |= 1;
- pci_write_config8(PCH_DEV_LPC, GEN_PMCON_3, reg8);
+ pci_or_config8(PCH_DEV_LPC, GEN_PMCON_3, 1);
/* also iterates over all bridges on bus 0 */
busmaster_disable_on_bus(0);
diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c
index 18f171d..90d2f7a 100644
--- a/src/southbridge/intel/common/smihandler.c
+++ b/src/southbridge/intel/common/smihandler.c
@@ -93,20 +93,25 @@
{
}
-static void southbridge_smi_sleep(void)
+static int power_on_after_fail(void)
{
- u8 reg8;
- u32 reg32;
- u8 slp_typ;
u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
- // save and recover RTC port values
+ /* save and recover RTC port values */
u8 tmp70, tmp72;
tmp70 = inb(0x70);
tmp72 = inb(0x72);
get_option(&s5pwr, "power_on_after_fail");
outb(tmp70, 0x70);
outb(tmp72, 0x72);
+ return (s5pwr == MAINBOARD_POWER_ON);
+}
+
+static void southbridge_smi_sleep(void)
+{
+ u8 reg8;
+ u32 reg32;
+ u8 slp_typ;
/* First, disable further SMIs */
write_pmbase8(SMI_EN, read_pmbase8(SMI_EN) & ~SLP_SMI_EN);
@@ -156,13 +161,10 @@
/* Always set the flag in case CMOS was changed on runtime. For
* "KEEP", switch to "OFF" - KEEP is software emulated
*/
- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), D31F0_GEN_PMCON_3);
- if (s5pwr == MAINBOARD_POWER_ON) {
- reg8 &= ~1;
- } else {
- reg8 |= 1;
- }
- pci_write_config8(PCI_DEV(0, 0x1f, 0), D31F0_GEN_PMCON_3, reg8);
+ if (power_on_after_fail())
+ pci_and_config8(PCI_DEV(0, 0x1f, 0), D31F0_GEN_PMCON_3, ~1);
+ else
+ pci_or_config8(PCI_DEV(0, 0x1f, 0), D31F0_GEN_PMCON_3, 1);
/* also iterates over all bridges on bus 0 */
busmaster_disable_on_bus(0);
diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c
index 5e31808..948e216 100644
--- a/src/southbridge/intel/lynxpoint/smihandler.c
+++ b/src/southbridge/intel/lynxpoint/smihandler.c
@@ -76,13 +76,9 @@
}
}
-static void southbridge_smi_sleep(void)
+static int power_on_after_fail(void)
{
- u8 reg8;
- u32 reg32;
- u8 slp_typ;
u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
- u16 pmbase = get_pmbase();
/* save and recover RTC port values */
u8 tmp70, tmp72;
@@ -91,6 +87,15 @@
get_option(&s5pwr, "power_on_after_fail");
outb(tmp70, 0x70);
outb(tmp72, 0x72);
+ return (s5pwr == MAINBOARD_POWER_ON);
+}
+
+static void southbridge_smi_sleep(void)
+{
+ u8 reg8;
+ u32 reg32;
+ u8 slp_typ;
+ u16 pmbase = get_pmbase();
/* First, disable further SMIs */
disable_smi(SLP_SMI_EN);
@@ -142,12 +147,10 @@
/* Always set the flag in case CMOS was changed on runtime. For
* "KEEP", switch to "OFF" - KEEP is software emulated
*/
- reg8 = pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3);
- if (s5pwr == MAINBOARD_POWER_ON)
- reg8 &= ~1;
+ if (power_on_after_fail())
+ pci_and_config8(PCH_DEV_LPC, GEN_PMCON_3, ~1);
else
- reg8 |= 1;
- pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, reg8);
+ pci_or_config8(PCH_DEV_LPC, GEN_PMCON_3, 1);
/* also iterates over all bridges on bus 0 */
busmaster_disable_on_bus(0);
To view, visit change 49251. To unsubscribe, or for help writing mail filters, visit settings.