Werner Zeh merged this change.

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Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved
siemens/mc_apl1: Activate clock spreading for PTN3460

In order to minimize Electromagnetic Interference (EMI) on the LVDS
interface driven by PTN3460, clock spreading must be activated for
mc_apl1 mainboard. The modulation ratio is set to 1 % of the nominal
frequency.

Change-Id: Ie457fcdbb6239dc0b25e2c35ad7a310ee80383f9
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/28761
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
M src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c
index f1cbf0f..829af2a 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c
@@ -84,8 +84,8 @@
/* Use 18 bits per pixel. */
cfg.lvds_interface_ctrl1 |= 0x20;

- /* No clock spreading, 300 mV LVDS swing. */
- cfg.lvds_interface_ctrl2 = 0x03;
+ /* 1 % clock spreading, 300 mV LVDS swing. */
+ cfg.lvds_interface_ctrl2 = 0x13;
/* No LVDS signal swap. */
cfg.lvds_interface_ctrl3 = 0x00;
/* Delay T2 (VDD to LVDS active) by 16 ms. */

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: Ie457fcdbb6239dc0b25e2c35ad7a310ee80383f9
Gerrit-Change-Number: 28761
Gerrit-PatchSet: 4
Gerrit-Owner: Mario Scheithauer <mario.scheithauer@siemens.com>
Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer@siemens.com>
Gerrit-Reviewer: Werner Zeh <werner.zeh@siemens.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>