Jonathan Zhang has uploaded this change for review.
soc/intel/xeon_sp/cpx: skip DRHD generation for non-PCIe stack
This is a temporary patch to unblock test/release. It will be replaced
by following patches:
* A patch to correct ioapic GSIs.
* A patch to skip DRHD generation for non-PCIe stack (this can only be
done when the IPS ticket is resolved).
With the patch to correct ioapic GSIs, there are following target OS
boot errors:
[ 1.098771] IOAPIC[0]: apic_id 8, version 32, address 0xfec00000, GSI 0-119
[ 1.099159] GSI range [24-31] for new IOAPIC conflicts with GSI[0-119]
With the patch, these are the messages:
[ 0.399498] IOAPIC[0]: apic_id 8, version 32, address 0xfec00000, GSI 0-119
[ 0.399848] IOAPIC[1]: apic_id 9, version 32, address 0xfec01000, GSI 120-127
I also suspect this causes the reboot instability issue. During some
reboots (like once every 30 reboots), following failures happen:
[ 4.325795] mce: [Hardware Error]: Machine check events logged
[ 4.326597] mce: [Hardware Error]: CPU 0: Machine Check: 0 Bank 9: ee2000000003110a
[ 4.327594] mce: [Hardware Error]: TSC 0 ADDR fe9e0000 MISC 228aa040101086
[ 4.328596] mce: [Hardware Error]: PROCESSOR 0:5065b TIME 1601443875 SOCKET 0 APIC 0 microcode 700001d
The MCE errors is happen in bank 9, 10 and 11. The Model specific error code
shows it is about SAD_ERR_WB_TO_MMIO error (doc 604926), which means something
goes wrong when cache write back to mmio. It is a generic transaction type error
in level 2.
Since the error happens during smpboot of PBSP, I suspect this is an issue
related to ioapic, hence found the issue with MADT table.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I098605daf12a264f390613581427ec722afcddaf
---
M src/soc/intel/xeon_sp/cpx/acpi.c
1 file changed, 19 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/45887/1
diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c
index cd497c5..8792131 100644
--- a/src/soc/intel/xeon_sp/cpx/acpi.c
+++ b/src/soc/intel/xeon_sp/cpx/acpi.c
@@ -187,7 +187,7 @@
int cur_index;
struct iiostack_resource stack_info = {0};
- int gsi_bases[] = { 0, 0x18, 0x20, 0x28, 0x30, 0x48, 0x50, 0x58, 0x60 };
+ int gsi_bases[] = { 0, 0x78, 0x80, 0x88, 0x90, 0x98, 0xA0, 0xA8, 0xB0 };
int ioapic_ids[] = { 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0x10, 0x11, 0x12 };
/* Local APICs */
@@ -612,9 +612,20 @@
if (get_stack_for_port(port) != stack)
return 0;
- const uint32_t bus = iio_resource.StackRes[stack].BusBase;
- const uint32_t dev = iio_resource.PcieInfo.PortInfo[port].Device;
- const uint32_t func = iio_resource.PcieInfo.PortInfo[port].Function;
+ uint32_t bus = iio_resource.StackRes[stack].BusBase;
+ uint32_t dev = iio_resource.PcieInfo.PortInfo[port].Device;
+ uint32_t func = iio_resource.PcieInfo.PortInfo[port].Function;
+
+ /* TODO: remove this workaround when the IPS ticket is resolved. */
+ if (port == PORT_1A || port == PORT_2A || port == PORT_3A)
+ dev = 0x0;
+ else if (port == PORT_1B || port == PORT_2B || port == PORT_3B)
+ dev = 0x1;
+ else if (port == PORT_1C || port == PORT_2C || port == PORT_3C)
+ dev = 0x2;
+ else if (port == PORT_1D || port == PORT_2D || port == PORT_3D)
+ dev = 0x3;
+ func = 0x0;
const uint32_t id = pci_mmio_read_config32(PCI_DEV(bus, dev, func),
PCI_VENDOR_ID);
@@ -660,6 +671,10 @@
printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, pcie_seg: 0x%x, reg_base: 0x%x\n",
__func__, socket, stack, bus, pcie_seg, reg_base);
+ /* Do not generate DRHD for non-PCIe stack */
+ if (reg_base == 0x0)
+ return current;
+
// Add DRHD Hardware Unit
if (socket == 0 && stack == CSTACK) {
printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, "
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