Felix Singer has uploaded this change for review.

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soc/intel/cnl: GNA

Change-Id: I921e29bfc77c8096519b52fec8bb6b2193006f99
Signed-off-by: Felix Singer <felix.singer@secunet.com>
---
M src/soc/intel/cannonlake/fsp_params.c
M src/soc/intel/cannonlake/include/soc/pci_devs.h
2 files changed, 7 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/44739/1

diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 51ed2a8..95da672 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -643,6 +643,9 @@
 		params->PeiGraphicsPeimInit = 1;
 	else
 		params->PeiGraphicsPeimInit = 0;
+
+	dev = pcidev_path_on_root(SA_DEVFN_GNA);
+	params->GnaEnable = is_dev_enabled(dev);
 }
 
 /* Mainboard GPIO Configuration */
diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h
index c9c51ca..fd43bbd 100644
--- a/src/soc/intel/cannonlake/include/soc/pci_devs.h
+++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h
@@ -34,6 +34,10 @@
 #define  SA_DEVFN_IPU		PCI_DEVFN(SA_DEV_SLOT_IPU, 0)
 #define  SA_DEV_IPU		PCI_DEV(0, SA_DEV_SLOT_IPU, 0)
 
+#define SA_DEV_SLOT_GNA		0x08
+#define  SA_DEVFN_GNA		PCI_DEVFN(SA_DEV_SLOT_GNA, 0)
+#define  SA_DEV_GNA		PCI_DEV(0, SA_DEV_SLOT_GNA, 0)
+
 /* PCH Devices */
 #define PCH_DEV_SLOT_THERMAL	0x12
 #define  PCH_DEVFN_THERMAL	_PCH_DEVFN(THERMAL, 0)

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