Michael has uploaded this change for review.
superio/ite: allow 24 MHz clock for external sensor interface
The interface selection register of the environment controller (EC)
gives the choice between "Internal generated 32 MHz" and "24 MHz" for
the "SST/PECI Host Controller Clock Selection".
Previously the chip was always configured for the 32 MHz clock. Add an
option that can be set from devicetree.cb to allow using the 24 MHz
clock.
Without this setting the automatic fan control on an Acer Aspire M3800
was slow to respond to temperature changes.
Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Change-Id: Ib2bce10a828fb4a7d837f6c5f5b1d00cc51be0ce
---
M src/superio/ite/common/env_ctrl.c
M src/superio/ite/common/env_ctrl_chip.h
2 files changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/44166/1
diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c
index 52981ec..a281ab6 100644
--- a/src/superio/ite/common/env_ctrl.c
+++ b/src/superio/ite/common/env_ctrl.c
@@ -262,6 +262,13 @@
ITE_EC_INTERFACE_SMB_ENABLE);
}
+ /* Set SST/PECI Host Controller Clock to either 24 MHz or internal 32 MHz */
+ if (conf->smbus_24mhz) {
+ pnp_write_hwm5_index(base, ITE_EC_INTERFACE_SELECT,
+ pnp_read_hwm5_index(base, ITE_EC_INTERFACE_SELECT) |
+ ITE_EC_INTERFACE_CLOCK_24MHZ);
+ }
+
/* Enable reading of voltage pins */
pnp_write_hwm5_index(base, ITE_EC_ADC_VOLTAGE_CHANNEL_ENABLE, conf->vin_mask);
diff --git a/src/superio/ite/common/env_ctrl_chip.h b/src/superio/ite/common/env_ctrl_chip.h
index 5f824be..149832d 100644
--- a/src/superio/ite/common/env_ctrl_chip.h
+++ b/src/superio/ite/common/env_ctrl_chip.h
@@ -92,6 +92,11 @@
* Enable SMBus for external thermal sensor.
*/
bool smbus_en;
+ /*
+ * Select 24 MHz clock for external host instead of an
+ * internally generated 32 MHz clock.
+ */
+ bool smbus_24mhz;
};
/* Some shorthands for device trees */
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