[coreboot-gerrit] Patch merged into coreboot/master: rockchip: spi: Set rxd sample delay when using high speed

the following patch was just integrated into master:
commit 52669fc4dc4ab38e9ca61d65487fdfb809d3dd3d
Author: Simon Glass 
Date:   Mon Sep 5 11:04:50 2016 -0600

rockchip: spi: Set rxd sample delay when using high speed

At higher SPI bus speeds the SPI RX value is not available in time for
    sampling at the normal time. Add a delay to ensure that we read the
    correct data.

The value of 40ns is chosen arbitrarily. In my testing I can use a sample
    delay of 1 even at 24MHz. But since it is not necessary, I have left that
    case alone. It kicks in at 25MHz and up.

BUG=chrome-os-partner:56556
    BRANCH=none
    TEST=boot on gru and see no change at current speed

Change-Id: I3ef335d9a532eaef1e76034bd02e185acf11176a
    Signed-off-by: Patrick Georgi 
    Original-Commit-Id: e9b620c47fc3e39211487507fadb8657afdebee7
    Original-Change-Id: I65d66d752cbbbee4d02f475de23a52069a0e9782
    Original-Signed-off-by: Simon Glass 
    Original-Reviewed-on: https://chromium-review.googlesource.com/381311
    Original-Commit-Ready: Julius Werner 
    Original-Tested-by: Simon Glass 
    Original-Reviewed-by: Julius Werner 
    Reviewed-on: https://review.coreboot.org/16707
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi

See https://review.coreboot.org/16707 for details.

-gerrit