Duncan Laurie has uploaded this change for review.
soc/intel: Enable GPIO functions in verstage
Enable GPIO functionality in verstage so platforms can read a
PCH GPIO in verstage to determine recovery mode.
Change-Id: Icd4344c4d66dbe21fda9dc27e61a836c1dd9be07
Signed-off-by: Duncan Laurie <dlaurie@google.com>
---
M src/soc/intel/cannonlake/Makefile.inc
M src/soc/intel/common/block/gpio/Makefile.inc
M src/soc/intel/common/block/pcr/Makefile.inc
3 files changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/29407/1
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index e95d04f..2452f50 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -77,11 +77,13 @@
romstage-y += gpio_cnp_h.c
ramstage-y += gpio_cnp_h.c
smm-y += gpio_cnp_h.c
+verstage-y += gpio_cnp_h.c
else
bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-y += gpio.c
smm-y += gpio.c
+verstage-y += gpio.c
endif
CPPFLAGS_common += -I$(src)/soc/intel/cannonlake
diff --git a/src/soc/intel/common/block/gpio/Makefile.inc b/src/soc/intel/common/block/gpio/Makefile.inc
index bf40397..b0ffee3 100644
--- a/src/soc/intel/common/block/gpio/Makefile.inc
+++ b/src/soc/intel/common/block/gpio/Makefile.inc
@@ -2,3 +2,4 @@
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c
romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c
smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c
+verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c
diff --git a/src/soc/intel/common/block/pcr/Makefile.inc b/src/soc/intel/common/block/pcr/Makefile.inc
index c64fe7a..0577e0a 100644
--- a/src/soc/intel/common/block/pcr/Makefile.inc
+++ b/src/soc/intel/common/block/pcr/Makefile.inc
@@ -2,3 +2,4 @@
romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c
smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c
+verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c
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