Michał Żygowski has uploaded this change for review.
commonlib/elog: Add missing PCI Express PME sources
Intel Skylake SoC defines more than 12 PCI Express wake sources.
However, these wake sources are not defined anywhere. Without these
definitions the coreboot build for Skylake or Kaby Lake board fails
when event log is enabled.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ie60a232104d8947d86de5add150f12ba7c03b0cc
---
M src/commonlib/include/commonlib/elog.h
1 file changed, 24 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/40417/1
diff --git a/src/commonlib/include/commonlib/elog.h b/src/commonlib/include/commonlib/elog.h
index 3b84242..c9b0c3e 100644
--- a/src/commonlib/include/commonlib/elog.h
+++ b/src/commonlib/include/commonlib/elog.h
@@ -166,6 +166,18 @@
#define ELOG_WAKE_SOURCE_PME_XHCI_USB_2 0x1d
#define ELOG_WAKE_SOURCE_PME_XHCI_USB_3 0x1e
#define ELOG_WAKE_SOURCE_PME_WIFI 0x1f
+#define ELOG_WAKE_SOURCE_PME_PCIE13 0x20
+#define ELOG_WAKE_SOURCE_PME_PCIE14 0x21
+#define ELOG_WAKE_SOURCE_PME_PCIE15 0x22
+#define ELOG_WAKE_SOURCE_PME_PCIE16 0x23
+#define ELOG_WAKE_SOURCE_PME_PCIE17 0x24
+#define ELOG_WAKE_SOURCE_PME_PCIE18 0x25
+#define ELOG_WAKE_SOURCE_PME_PCIE19 0x26
+#define ELOG_WAKE_SOURCE_PME_PCIE20 0x27
+#define ELOG_WAKE_SOURCE_PME_PCIE21 0x28
+#define ELOG_WAKE_SOURCE_PME_PCIE22 0x29
+#define ELOG_WAKE_SOURCE_PME_PCIE23 0x2a
+#define ELOG_WAKE_SOURCE_PME_PCIE24 0x2b
struct elog_event_data_wake {
uint8_t source;
@@ -383,6 +395,18 @@
{ ELOG_WAKE_SOURCE_PME_PCIE10, "PCI Express 10 PME" },
{ ELOG_WAKE_SOURCE_PME_PCIE11, "PCI Express 11 PME" },
{ ELOG_WAKE_SOURCE_PME_PCIE12, "PCI Express 12 PME" },
+ { ELOG_WAKE_SOURCE_PME_PCIE13, "PCI Express 13 PME" },
+ { ELOG_WAKE_SOURCE_PME_PCIE14, "PCI Express 14 PME" },
+ { ELOG_WAKE_SOURCE_PME_PCIE15, "PCI Express 15 PME" },
+ { ELOG_WAKE_SOURCE_PME_PCIE16, "PCI Express 16 PME" },
+ { ELOG_WAKE_SOURCE_PME_PCIE17, "PCI Express 17 PME" },
+ { ELOG_WAKE_SOURCE_PME_PCIE18, "PCI Express 18 PME" },
+ { ELOG_WAKE_SOURCE_PME_PCIE19, "PCI Express 19 PME" },
+ { ELOG_WAKE_SOURCE_PME_PCIE20, "PCI Express 20 PME" },
+ { ELOG_WAKE_SOURCE_PME_PCIE21, "PCI Express 21 PME" },
+ { ELOG_WAKE_SOURCE_PME_PCIE22, "PCI Express 22 PME" },
+ { ELOG_WAKE_SOURCE_PME_PCIE23, "PCI Express 23 PME" },
+ { ELOG_WAKE_SOURCE_PME_PCIE24, "PCI Express 24 PME" },
{ ELOG_WAKE_SOURCE_PME_SATA, "SATA PME" },
{ ELOG_WAKE_SOURCE_PME_CSE, "CSE PME" },
{ ELOG_WAKE_SOURCE_PME_CSE2, "CSE 2 PME" },
To view, visit change 40417. To unsubscribe, or for help writing mail filters, visit settings.