Matt Parnell has uploaded this change for review.
WIP: add src/ec/hp/it8987e
Signed-off-by: Matt Parnell <mparnell@gmail.com>
Change-Id: I13c17269d1aecf530648a2f2eb5ff8ae3101f455
---
A src/ec/hp/it8987e/Kconfig
A src/ec/hp/it8987e/Makefile.inc
A src/ec/hp/it8987e/acpi/ac.asl
A src/ec/hp/it8987e/acpi/battery.asl
A src/ec/hp/it8987e/acpi/ec.asl
A src/ec/hp/it8987e/acpi/kb.asl
A src/ec/hp/it8987e/acpi/superio.asl
A src/ec/hp/it8987e/acpi/tpm.asl
A src/ec/hp/it8987e/chip.h
A src/ec/hp/it8987e/ec.c
A src/ec/hp/it8987e/ec.h
11 files changed, 2,498 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/34984/1
diff --git a/src/ec/hp/it8987e/Kconfig b/src/ec/hp/it8987e/Kconfig
new file mode 100644
index 0000000..54f7896
--- /dev/null
+++ b/src/ec/hp/it8987e/Kconfig
@@ -0,0 +1,4 @@
+config EC_HP_IT8987E
+ bool
+ help
+ Interface to QUANTA/HP IT8987E Embedded Controller.
diff --git a/src/ec/hp/it8987e/Makefile.inc b/src/ec/hp/it8987e/Makefile.inc
new file mode 100644
index 0000000..db11205
--- /dev/null
+++ b/src/ec/hp/it8987e/Makefile.inc
@@ -0,0 +1,8 @@
+ifeq ($(CONFIG_EC_HP_IT8987E),y)
+
+romstage-y += ec.c
+ramstage-y += ec.c
+smm-y += ec.c
+smm-y += ../../../lib/delay.c
+
+endif
diff --git a/src/ec/hp/it8987e/acpi/ac.asl b/src/ec/hp/it8987e/acpi/ac.asl
new file mode 100644
index 0000000..bb4b4fe
--- /dev/null
+++ b/src/ec/hp/it8987e/acpi/ac.asl
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+// Scope (EC0)
+
+Device (AC)
+{
+ Name (_HID, "ACPI0003")
+ Name (_PCL, Package () { \_SB })
+
+ Method (_PSR, 0, NotSerialized) // _PSR: Power Source
+ {
+ If ((^^PCI0.LPCB.EC0.ECOK == One))
+ {
+ Local0 = ^^PCI0.LPCB.EC0.SW2S
+ }
+ Else
+ {
+ Local0 = One
+ }
+
+ Return (Local0)
+ }
+
+ Method (_STA)
+ {
+ Return (0x0F)
+ }
+}
diff --git a/src/ec/hp/it8987e/acpi/battery.asl b/src/ec/hp/it8987e/acpi/battery.asl
new file mode 100644
index 0000000..5b25609
--- /dev/null
+++ b/src/ec/hp/it8987e/acpi/battery.asl
@@ -0,0 +1,252 @@
+/*
+* This file is part of the coreboot project.
+*
+* Copyright (C) 2013 Google Inc.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; version 2 of
+* the License.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*/
+
+Device (BAT0)
+{
+ Name (FRST, One)
+ Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_PCL, Package (0x01) // _PCL: Power Consumer List
+ {
+ _SB
+ })
+ Name (PBIF, Package (0x0D)
+ {
+ One,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ One,
+ 0xFFFFFFFF,
+ 0xFA,
+ 0x96,
+ 0x0A,
+ 0x19,
+ "BAT0",
+ " ",
+ " ",
+ " "
+ })
+ Name (PBST, Package (0x04)
+ {
+ Zero,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0x2710
+ })
+ Name (BAST, Zero)
+ Name (B1ST, 0x0F)
+ Name (B1WT, Zero)
+ Name (FABL, 0xFFFFFFFF)
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If ((^^PCI0.LPCB.EC0.ECOK == One))
+ {
+ If (^^PCI0.LPCB.EC0.MBTS)
+ {
+ B1ST = 0x1F
+ }
+ Else
+ {
+ B1ST = 0x0F
+ }
+ }
+ Else
+ {
+ B1ST = 0x0F
+ }
+
+ Return (B1ST) /* \_SB_.BAT0.B1ST */
+ }
+
+ Method (_BIF, 0, NotSerialized) // _BIF: Battery Information
+ {
+ If ((^^PCI0.LPCB.EC0.ECOK == One))
+ {
+ If (^^PCI0.LPCB.EC0.MBTS)
+ {
+ UPBI ()
+ }
+ Else
+ {
+ IVBI ()
+ }
+ }
+ Else
+ {
+ IVBI ()
+ }
+
+ Return (PBIF) /* \_SB_.BAT0.PBIF */
+ }
+
+ Method (_BST, 0, NotSerialized) // _BST: Battery Status
+ {
+ If ((^^PCI0.LPCB.EC0.ECOK == One))
+ {
+ If (^^PCI0.LPCB.EC0.MBTS)
+ {
+ UPBS ()
+ }
+ Else
+ {
+ IVBS ()
+ }
+ }
+ Else
+ {
+ IVBS ()
+ }
+
+ Return (PBST) /* \_SB_.BAT0.PBST */
+ }
+
+ Method (UPBI, 0, NotSerialized)
+ {
+ Local5 = ^^PCI0.LPCB.EC0.BFCC /* \_SB_.PCI0.LPCB.EC0_.BFCC */
+ If ((Local5 && !(Local5 & 0x8000)))
+ {
+ Local5 >>= 0x05
+ Local5 <<= 0x05
+ PBIF [One] = Local5
+ PBIF [0x02] = Local5
+ Local2 = (Local5 / 0x64)
+ Local2 += One
+ If ((^^PCI0.LPCB.EC0.BADC < 0x0C80))
+ {
+ Local4 = (Local2 * 0x0E)
+ PBIF [0x05] = (Local4 + 0x02)
+ Local4 = (Local2 * 0x09)
+ PBIF [0x06] = (Local4 + 0x02)
+ Local4 = (Local2 * 0x0B)
+ }
+ ElseIf ((SMA4 == One))
+ {
+ Local4 = (Local2 * 0x0A)
+ PBIF [0x05] = (Local4 + 0x02)
+ Local4 = (Local2 * 0x05)
+ PBIF [0x06] = (Local4 + 0x02)
+ Local4 = (Local2 * 0x08)
+ }
+ Else
+ {
+ Local4 = (Local2 * 0x0C)
+ PBIF [0x05] = (Local4 + 0x02)
+ Local4 = (Local2 * 0x07)
+ PBIF [0x06] = (Local4 + 0x02)
+ Local4 = (Local2 * 0x0A)
+ }
+
+ FABL = (Local4 + 0x02)
+ }
+
+ Local0 = ^^PCI0.LPCB.EC0.BVLB /* \_SB_.PCI0.LPCB.EC0_.BVLB */
+ Local1 = ^^PCI0.LPCB.EC0.BVHB /* \_SB_.PCI0.LPCB.EC0_.BVHB */
+ Local1 <<= 0x08
+ Local0 |= Local1
+ PBIF [0x04] = Local0
+ Sleep (0x32)
+ PBIF [0x0B] = "LION"
+ PBIF [0x09] = "Primary"
+ UPUM ()
+ PBIF [Zero] = One
+ }
+
+ Method (UPUM, 0, NotSerialized)
+ {
+ Local0 = Buffer (0x0A)
+ {
+ /* 0000 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........
+ /* 0008 */ 0x00, 0x00 // ..
+ }
+ Local6 = Buffer (0x05)
+ {
+ 0x36, 0x35, 0x35, 0x33, 0x35 // 65535
+ }
+ Local7 = Buffer (0x05)
+ {
+ 0x31, 0x32, 0x33, 0x32, 0x31 // 12321
+ }
+ PBIF [0x0C] = "HP"
+ }
+
+ Method (UPBS, 0, NotSerialized)
+ {
+ If ((BRTM == One))
+ {
+ Local0 = ^^PCI0.LPCB.EC0.MCUR /* \_SB_.PCI0.LPCB.EC0_.MCUR */
+ If ((Local0 & 0x8000))
+ {
+ If ((Local0 == 0xFFFF))
+ {
+ PBST [One] = 0xFFFFFFFF
+ }
+ Else
+ {
+ Local1 = ~Local0
+ Local1++
+ Local3 = (Local1 & 0xFFFF)
+ PBST [One] = Local3
+ }
+ }
+ Else
+ {
+ PBST [One] = Local0
+ }
+ }
+ Else
+ {
+ PBST [One] = 0xFFFFFFFF
+ }
+
+ Local5 = ^^PCI0.LPCB.EC0.MBRM /* \_SB_.PCI0.LPCB.EC0_.MBRM */
+ If (!(Local5 & 0x8000))
+ {
+ Local5 >>= 0x05
+ Local5 <<= 0x05
+ If ((Local5 != DerefOf (PBST [0x02])))
+ {
+ PBST [0x02] = Local5
+ }
+ }
+
+ If ((!^^PCI0.LPCB.EC0.SW2S && (^^PCI0.LPCB.EC0.BACR == One)))
+ {
+ PBST [0x02] = FABL /* \_SB_.BAT0.FABL */
+ }
+
+ PBST [0x03] = ^^PCI0.LPCB.EC0.MBCV /* \_SB_.PCI0.LPCB.EC0_.MBCV */
+ PBST [Zero] = ^^PCI0.LPCB.EC0.MBST /* \_SB_.PCI0.LPCB.EC0_.MBST */
+ }
+
+ Method (IVBI, 0, NotSerialized)
+ {
+ PBIF [One] = 0xFFFFFFFF
+ PBIF [0x02] = 0xFFFFFFFF
+ PBIF [0x04] = 0xFFFFFFFF
+ PBIF [0x09] = "Bad"
+ PBIF [0x0A] = "Bad"
+ PBIF [0x0B] = "Bad"
+ PBIF [0x0C] = "Bad"
+ }
+
+ Method (IVBS, 0, NotSerialized)
+ {
+ PBST [Zero] = Zero
+ PBST [One] = 0xFFFFFFFF
+ PBST [0x02] = 0xFFFFFFFF
+ PBST [0x03] = 0x2710
+ }
+}
diff --git a/src/ec/hp/it8987e/acpi/ec.asl b/src/ec/hp/it8987e/acpi/ec.asl
new file mode 100644
index 0000000..8f039d1
--- /dev/null
+++ b/src/ec/hp/it8987e/acpi/ec.asl
@@ -0,0 +1,1201 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * The mainboard must define a PNOT method to handle power
+ * state notifications and Notify CPU device objects to
+ * re-evaluate their _PPC and _CST tables.
+ */
+
+Device (EC0)
+{
+ Name (_HID, EisaId ("PNP0C09") /* Embedded Controller Device */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (PHOT, One)
+ Name (ECAV, Zero)
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Name (BFFR, ResourceTemplate ()
+ {
+ IO (Decode16,
+ 0x0062, // Range Minimum
+ 0x0062, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0066, // Range Minimum
+ 0x0066, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ })
+ Return (BFFR) /* \_SB_.PCI0.LPCB.EC0_._CRS.BFFR */
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ ^^^GFX0.CLID = 0x03
+ Return (0x0F)
+ }
+
+ OperationRegion (ERAM, EmbeddedControl, Zero, 0xFF)
+ Field (ERAM, ByteAcc, NoLock, Preserve)
+ {
+ SMPR, 8,
+ SMST, 8,
+ SMAD, 8,
+ SMCM, 8,
+ SMD0, 256,
+ BCNT, 8,
+ SMAA, 8,
+ Offset (0x40),
+ SW2S, 1,
+ , 2,
+ ACCC, 1,
+ TRPM, 1,
+ Offset (0x41),
+ W7OS, 1,
+ QWOS, 1,
+ , 1,
+ SUSE, 1,
+ RFLG, 1,
+ Offset (0x43),
+ , 1,
+ , 1,
+ ACPS, 1,
+ ACKY, 1,
+ GFXT, 1,
+ Offset (0x44),
+ , 7,
+ DSMB, 1,
+ Offset (0x47),
+ TNT2, 8,
+ TNT3, 8,
+ Offset (0x4C),
+ STRM, 8,
+ Offset (0x4E),
+ LIDE, 1,
+ Offset (0x4F),
+ ACID, 8,
+ , 2,
+ PTHM, 1,
+ , 1,
+ BSEV, 1,
+ DPTL, 1,
+ Offset (0x52),
+ ECLS, 1,
+ Offset (0x55),
+ EC45, 8,
+ Offset (0x58),
+ RTMP, 8,
+ TNT1, 8,
+ Offset (0x5F),
+ , 1,
+ Offset (0x61),
+ SHPM, 8,
+ Offset (0x67),
+ , 1,
+ , 1,
+ GC6R, 1,
+ IGC6, 1,
+ , 2,
+ PVSE, 1,
+ PVSS, 1,
+ , 3,
+ PLGS, 1,
+ , 3,
+ TPDF, 1,
+ , 4,
+ BCTF, 1,
+ BMNF, 1,
+ BTVD, 1,
+ BF10, 1,
+ Offset (0x6C),
+ GWKR, 8,
+ Offset (0x70),
+ BADC, 16,
+ BFCC, 16,
+ BVLB, 8,
+ BVHB, 8,
+ BDVO, 8,
+ Offset (0x7F),
+ ECTB, 1,
+ Offset (0x82),
+ MBST, 8,
+ MCUR, 16,
+ MBRM, 16,
+ MBCV, 16,
+ Offset (0x8B),
+ LEDM, 3,
+ Offset (0x8D),
+ , 5,
+ MBFC, 1,
+ Offset (0x92),
+ SPSV, 8,
+ Offset (0x94),
+ GSSU, 1,
+ GSMS, 1,
+ Offset (0x95),
+ MMST, 4,
+ DMST, 4,
+ Offset (0xA0),
+ QBHK, 8,
+ Offset (0xA2),
+ QBBB, 8,
+ Offset (0xA4),
+ MBTS, 1,
+ , 6,
+ BACR, 1,
+ Offset (0xA6),
+ MBDC, 8,
+ Offset (0xA8),
+ ENWD, 1,
+ TMPR, 1,
+ Offset (0xAA),
+ , 1,
+ SMSZ, 1,
+ , 5,
+ RCDS, 1,
+ Offset (0xAD),
+ SADP, 8,
+ Offset (0xB2),
+ RPM1, 8,
+ RPM2, 8,
+ Offset (0xBA),
+ CLOW, 8,
+ CMAX, 8,
+ Offset (0xC1),
+ DPPC, 8,
+ Offset (0xC6),
+ , 1,
+ CVTS, 1,
+ Offset (0xCE),
+ NVDX, 8,
+ ECDX, 8,
+ EBPL, 1,
+ Offset (0xD2),
+ , 7,
+ DLYE, 1,
+ Offset (0xD4),
+ PSHD, 8,
+ PSLD, 8,
+ DBPL, 8,
+ STSP, 8,
+ Offset (0xDA),
+ PSIN, 8,
+ PSKB, 1,
+ PSTP, 1,
+ , 1,
+ PWOL, 1,
+ RTCE, 1,
+ Offset (0xE0),
+ DLYT, 8,
+ DLY2, 8,
+ Offset (0xE6),
+ SFHK, 8,
+ Offset (0xE9),
+ DTMT, 8,
+ PL12, 8,
+ ETMT, 8,
+ Offset (0xF2),
+ ZPDD, 1,
+ , 6,
+ ENPA, 1,
+ Offset (0xF4),
+ SFAN, 8,
+ Offset (0xF9),
+ , 7,
+ FTHM, 1
+ }
+
+ Name (ECOK, Zero)
+ Name (BATO, Zero)
+ Name (BATN, Zero)
+ Name (BATF, 0xC0)
+ Name (TMEE, Zero)
+ Name (TMDE, Zero)
+ Method (_REG, 2, NotSerialized) // _REG: Region Availability
+ {
+ If (((Arg0 == 0x03) && (Arg1 == One)))
+ {
+ ECOK = One
+ GBAS ()
+ ECMI ()
+ }
+ }
+
+ Method (_GPE, 0, NotSerialized) // _GPE: General Purpose Events
+ {
+ Local0 = GGPE (0x02020017)
+ Return (Local0)
+ }
+
+ Method (BPOL, 1, NotSerialized)
+ {
+ DBPL = Arg0
+ EBPL = One
+ }
+
+ Method (BPOM, 0, NotSerialized)
+ {
+ DBPL = Zero
+ EBPL = Zero
+ }
+
+ Method (GBAS, 0, NotSerialized)
+ {
+ If ((ECOK == One))
+ {
+ BATF = Zero
+ Local0 = MBTS /* \_SB_.PCI0.LPCB.EC0_.MBTS */
+ Local1 = SW2S /* \_SB_.PCI0.LPCB.EC0_.SW2S */
+ Local0 <<= 0x06
+ Local1 <<= One
+ If (((BATO & 0x40) != Local0))
+ {
+ BATF |= 0x40
+ }
+
+ If (((BATO & 0x02) != Local1))
+ {
+ BATF |= 0x02
+ }
+
+ BATO = Zero
+ BATO = (Local0 | Local1)
+ }
+ }
+
+ Method (_Q09, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ BPOM ()
+ GBAS ()
+ Notify (BAT0, 0x80) // Status Change
+ Notify (BAT0, 0x81) // Information Change
+ Notify (ADP1, 0x80) // Status Change
+ }
+
+ Method (_Q0D, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Debug = "_Q0D : Switch Display (Fn+F4)"
+ ^^^GFX0.GHDS (Zero)
+ Sleep (0xC8)
+ }
+
+ Method (_Q10, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Notify (^^^GFX0.DD1F, 0x87) // Device-Specific
+ }
+
+ Method (_Q11, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Notify (^^^GFX0.DD1F, 0x86) // Device-Specific
+ }
+
+ Method (_Q15, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Debug = "!!! Wireless Button pressed !!!"
+ If ((OSYS >= 0x07DC))
+ {
+ Notify (WLBT, 0x80) // Status Change
+ }
+ Else
+ {
+ If (BNLS)
+ {
+ BNLS = Zero
+ Local0 = One
+ }
+ Else
+ {
+ BNLS = One
+ Local0 = Zero
+ }
+
+ If ((^^^^WMID.WMIF == One))
+ {
+ If (((WWLS == One) & (WLDS == One)))
+ {
+ If (One)
+ {
+ SGOV (0x02070002, Local0)
+ }
+ Else
+ {
+ SGOV (0x01090008, Local0)
+ }
+ }
+
+ If (((WBTS == One) & (BTDS == One)))
+ {
+ If (One)
+ {
+ SGOV (0x0203000C, Local0)
+ }
+ Else
+ {
+ SGOV (0x0103000C, Local0)
+ }
+ }
+ }
+ Else
+ {
+ If ((WLDS == One))
+ {
+ If (One)
+ {
+ SGOV (0x02070002, Local0)
+ }
+ Else
+ {
+ SGOV (0x01090008, Local0)
+ }
+ }
+
+ If ((BTDS == One))
+ {
+ If (One)
+ {
+ SGOV (0x0203000C, Local0)
+ }
+ Else
+ {
+ SGOV (0x0103000C, Local0)
+ }
+ }
+ }
+ }
+ }
+
+ Method (_Q20, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ If ((ECOK == One))
+ {
+ GBAS ()
+ If ((0x40 & BATF))
+ {
+ Notify (BAT0, 0x81) // Information Change
+ }
+
+ Notify (BAT0, 0x80) // Status Change
+ If ((0x02 & BATF))
+ {
+ Notify (ADP1, 0x80) // Status Change
+ PWRS = SW2S /* \_SB_.PCI0.LPCB.EC0_.SW2S */
+ If (SW2S)
+ {
+ ^^^^WMID.GWEV (0x03, Zero)
+ }
+ }
+
+ PNOT ()
+ }
+ }
+
+ Method (_Q21, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ If ((ECOK == One))
+ {
+ If ((BCTF || BMNF))
+ {
+ ^^^^WMID.GWEV (0x12, One)
+ }
+ }
+ }
+
+ Method (_Q22, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ If ((ECOK == One))
+ {
+ BACR = Zero
+ Notify (BAT0, 0x80) // Status Change
+ }
+ }
+
+ Method (_Q2A, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Notify (BAT0, 0x81) // Information Change
+ Notify (BAT0, 0x80) // Status Change
+ }
+
+ Method (_Q33, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Local0 = ^^RTC.RTMN /* \_SB_.PCI0.LPCB.RTC_.RTMN */
+ FromBCD (Local0, Local0)
+ Local1 = ^^RTC.RTHR /* \_SB_.PCI0.LPCB.RTC_.RTHR */
+ FromBCD (Local1, Local1)
+ Local2 = ^^RTC.RTDY /* \_SB_.PCI0.LPCB.RTC_.RTDY */
+ Local3 = ^^RTC.RTSE /* \_SB_.PCI0.LPCB.RTC_.RTSE */
+ FromBCD (Local3, Local3)
+ If ((ECOK == One))
+ {
+ PSIN = 0xFF
+ Sleep (One)
+ PSLD = Local0
+ PSHD = Local1
+ PSIN = 0x1C
+ Sleep (One)
+ PSLD = Local2
+ PSHD = Local3
+ PSIN = 0x1D
+ }
+ }
+
+ Method (_Q34, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ If ((ECOK == One))
+ {
+ If ((ENWD == One))
+ {
+ TMPR = One
+ }
+ }
+ }
+
+ Method (_Q46, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ If ((ECOK == One))
+ {
+ If ((CVTS == One))
+ {
+ Local0 = 0x03
+ Local0 <<= 0x10
+ Local0 |= 0x03
+ ^^^^WFTE.WMDE (Zero, One, Local0)
+ Notify (VBPA, 0xCC) // Hardware-Specific
+ }
+
+ If ((CVTS == Zero))
+ {
+ Local0 = 0x02
+ Local0 <<= 0x10
+ Local0 |= 0x02
+ ^^^^WFTE.WMDE (Zero, One, Local0)
+ Notify (VBPA, 0xCD) // Hardware-Specific
+ }
+ }
+ }
+
+ Method (_Q49, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ If ((ECOK == One))
+ {
+ If ((PVSS == One))
+ {
+ If ((PVSE == One))
+ {
+ ^^^^WMID.GWEV (0x14, 0xFE)
+ }
+ Else
+ {
+ ^^^^WMID.GWEV (0x14, 0xFF)
+ }
+ }
+ }
+ }
+
+ Method (_Q4D, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ ^^^^WMID.GWEV (0x00020001, Zero)
+ }
+
+ Method (_Q6F, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ ^^^^WMID.GWEV (0x04, Zero)
+ }
+
+ Method (_Q70, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ SGOV (0x0204000A, Zero)
+ }
+
+ Method (_Q71, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ SGOV (0x0204000A, One)
+ }
+
+ Method (_Q80, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Sleep (0x14)
+ Notify (\_TZ.TZ01, 0x80) // Thermal Status Change
+ }
+
+ Method (_Q82, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Sleep (0x14)
+ Debug = "_Q82 : Temperature reachs for Turbo Mode OFF"
+ TMDE = One
+ Notify (\_TZ.TZ01, 0x80) // Thermal Status Change
+ }
+
+ Method (_Q83, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Sleep (0x14)
+ Debug = "_Q83 : Temperature reachs for Turbo Mode ON"
+ TMEE = One
+ Notify (\_TZ.TZ01, 0x80) // Thermal Status Change
+ }
+
+ Method (_Q84, 0, Serialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ If ((PHOT == One))
+ {
+ PHOT = 0x02
+ }
+ }
+
+ Method (_Q85, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Notify (B0D4, 0x90) // Device-Specific
+ }
+
+ Method (_Q86, 0, Serialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ If ((PHOT == One))
+ {
+ PHOT = 0x03
+ }
+ }
+
+ Method (_Q8A, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ If ((ECOK == One))
+ {
+ If (LIDE)
+ {
+ Debug = "_Q8A : LID Switch Event"
+ LIDE = Zero
+ Sleep (0x14)
+ Notify (LID0, 0x80) // Status Change
+ }
+ }
+ }
+
+ Method (_Q8E, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ If (CondRefOf (\_PR.PR00._PPC))
+ {
+ Local0 = \_PR.PR00._PPC ()
+ }
+
+ Local1 = (MPPP - One)
+ If ((Local0 < Local1))
+ {
+ Local0++
+ CPUS (Local0)
+ }
+
+ CLOW = Local0
+ }
+
+ Method (_Q8F, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ If (CondRefOf (\_PR.PR00._PPC))
+ {
+ Local0 = \_PR.PR00._PPC ()
+ }
+
+ If (Local0)
+ {
+ Local0--
+ CPUS (Local0)
+ }
+
+ CLOW = Local0
+ }
+
+ Method (_Q99, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ }
+
+ Method (_QA0, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ }
+
+ Method (_QA1, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ }
+
+ Method (_QE4, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Local1 = Zero
+ Local0 = PKPS /* \PKPS */
+ If ((Local0 > 0x80))
+ {
+ Local0 -= 0x80
+ While ((Local0 > 0x06))
+ {
+ Local0 -= 0x10
+ Local1 += 0x06
+ }
+
+ Local1 += Local0
+ If (((Local1 >= 0x07) & (Local1 <= 0x0C)))
+ {
+ Local1 += 0x12
+ }
+ ElseIf (((Local1 >= 0x0D) & (Local1 <= 0x12)))
+ {
+ Local1 += 0x06
+ }
+ ElseIf (((Local1 >= 0x13) & (Local1 <= 0x18)))
+ {
+ Local1 -= 0x0C
+ }
+ ElseIf (((Local1 >= 0x19) & (Local1 <= 0x1E)))
+ {
+ Local1 -= 0x0C
+ }
+
+ Stall (0x05)
+ Local0 = Zero
+ Local3 = OFDA /* \OFDA */
+ While ((Local1 > One))
+ {
+ Local2 = DerefOf (Local3 [Local0])
+ Local0 += Local2
+ Local1 -= One
+ }
+
+ Stall (0x0F)
+ Local1 = DerefOf (Local3 [Local0])
+ Local2 = Zero
+ Stall (0x0F)
+ Name (KPFT, Buffer (0xA0){})
+ While ((Local2 < 0xA0))
+ {
+ If ((Local1 > Zero))
+ {
+ KPFT [Local2] = DerefOf (Local3 [Local0])
+ Local0++
+ Local1 -= One
+ }
+ Else
+ {
+ KPFT [Local2] = Zero
+ }
+
+ Local2++
+ Stall (0x05)
+ }
+
+ PKMC = KPFT /* \_SB_.PCI0.LPCB.EC0_._QE4.KPFT */
+ PKWD = One
+ }
+ }
+
+ Method (_QE5, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ ^^^^WMID.GWEV (0x12, PKPS)
+ }
+
+ Field (ERAM, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x04),
+ SMW0, 16
+ }
+
+ Field (ERAM, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x04),
+ SMB0, 8
+ }
+
+ Field (ERAM, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x04),
+ FLD0, 64
+ }
+
+ Field (ERAM, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x04),
+ FLD1, 128
+ }
+
+ Field (ERAM, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x04),
+ FLD2, 192
+ }
+
+ Field (ERAM, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x04),
+ FLD3, 256
+ }
+
+ Mutex (MUT0, 0x00)
+ Mutex (MUT1, 0x00)
+ Mutex (MUT2, 0x00)
+ Method (SMRD, 4, NotSerialized)
+ {
+ If (!ECOK)
+ {
+ Return (0xFF)
+ }
+
+ If ((Arg0 != 0x07))
+ {
+ If ((Arg0 != 0x09))
+ {
+ If ((Arg0 != 0x0B))
+ {
+ If ((Arg0 != 0x47))
+ {
+ If ((Arg0 != 0xC7))
+ {
+ Return (0x19)
+ }
+ }
+ }
+ }
+ }
+
+ Acquire (MUT0, 0xFFFF)
+ Local0 = 0x04
+ While ((Local0 > One))
+ {
+ SMST &= 0x40
+ SMCM = Arg2
+ SMAD = Arg1
+ SMPR = Arg0
+ Local3 = Zero
+ While (!Local1 = (SMST & 0xBF))
+ {
+ Sleep (0x02)
+ Local3++
+ If ((Local3 == 0x32))
+ {
+ SMST &= 0x40
+ SMCM = Arg2
+ SMAD = Arg1
+ SMPR = Arg0
+ Local3 = Zero
+ }
+ }
+
+ If ((Local1 == 0x80))
+ {
+ Local0 = Zero
+ }
+ Else
+ {
+ Local0--
+ }
+ }
+
+ If (Local0)
+ {
+ Local0 = (Local1 & 0x1F)
+ }
+ Else
+ {
+ If ((Arg0 == 0x07))
+ {
+ Arg3 = SMB0 /* \_SB_.PCI0.LPCB.EC0_.SMB0 */
+ }
+
+ If ((Arg0 == 0x47))
+ {
+ Arg3 = SMB0 /* \_SB_.PCI0.LPCB.EC0_.SMB0 */
+ }
+
+ If ((Arg0 == 0xC7))
+ {
+ Arg3 = SMB0 /* \_SB_.PCI0.LPCB.EC0_.SMB0 */
+ }
+
+ If ((Arg0 == 0x09))
+ {
+ Arg3 = SMW0 /* \_SB_.PCI0.LPCB.EC0_.SMW0 */
+ }
+
+ If ((Arg0 == 0x0B))
+ {
+ Local3 = BCNT /* \_SB_.PCI0.LPCB.EC0_.BCNT */
+ Local2 = 0x20
+ If ((Local3 > Local2))
+ {
+ Local3 = Local2
+ }
+
+ If ((Local3 < 0x11))
+ {
+ Local2 = FLD1 /* \_SB_.PCI0.LPCB.EC0_.FLD1 */
+ }
+ ElseIf ((Local3 < 0x19))
+ {
+ Local2 = FLD2 /* \_SB_.PCI0.LPCB.EC0_.FLD2 */
+ }
+ Else
+ {
+ Local2 = FLD3 /* \_SB_.PCI0.LPCB.EC0_.FLD3 */
+ }
+
+ Local3++
+ Local4 = Buffer (Local3){}
+ Local3--
+ Local5 = Zero
+ Name (OEMS, Buffer (0x46){})
+ ToBuffer (Local2, OEMS) /* \_SB_.PCI0.LPCB.EC0_.SMRD.OEMS */
+ While ((Local3 > Local5))
+ {
+ GBFE (OEMS, Local5, RefOf (Local6))
+ PBFE (Local4, Local5, Local6)
+ Local5++
+ }
+
+ PBFE (Local4, Local5, Zero)
+ Arg3 = Local4
+ }
+ }
+
+ Release (MUT0)
+ Return (Local0)
+ }
+
+ Method (SMWR, 4, NotSerialized)
+ {
+ If (!ECOK)
+ {
+ Return (0xFF)
+ }
+
+ If ((Arg0 != 0x06))
+ {
+ If ((Arg0 != 0x08))
+ {
+ If ((Arg0 != 0x0A))
+ {
+ If ((Arg0 != 0x46))
+ {
+ If ((Arg0 != 0xC6))
+ {
+ Return (0x19)
+ }
+ }
+ }
+ }
+ }
+
+ Acquire (MUT0, 0xFFFF)
+ Local0 = 0x04
+ While ((Local0 > One))
+ {
+ If ((Arg0 == 0x06))
+ {
+ SMB0 = Arg3
+ }
+
+ If ((Arg0 == 0x46))
+ {
+ SMB0 = Arg3
+ }
+
+ If ((Arg0 == 0xC6))
+ {
+ SMB0 = Arg3
+ }
+
+ If ((Arg0 == 0x08))
+ {
+ SMW0 = Arg3
+ }
+
+ If ((Arg0 == 0x0A))
+ {
+ SMD0 = Arg3
+ }
+
+ SMST &= 0x40
+ SMCM = Arg2
+ SMAD = Arg1
+ SMPR = Arg0
+ Local3 = Zero
+ While (!Local1 = (SMST & 0xBF))
+ {
+ Sleep (0x02)
+ Local3++
+ If ((Local3 == 0x32))
+ {
+ SMST &= 0x40
+ SMCM = Arg2
+ SMAD = Arg1
+ SMPR = Arg0
+ Local3 = Zero
+ }
+ }
+
+ If ((Local1 == 0x80))
+ {
+ Local0 = Zero
+ }
+ Else
+ {
+ Local0--
+ }
+ }
+
+ If (Local0)
+ {
+ Local0 = (Local1 & 0x1F)
+ }
+
+ Release (MUT0)
+ Return (Local0)
+ }
+
+ Method (GSHK, 0, Serialized)
+ {
+ If ((ECOK == One))
+ {
+ Local0 = SFHK /* \_SB_.PCI0.LPCB.EC0_.SFHK */
+ }
+
+ Return (Local0)
+ }
+
+ Method (SSHK, 1, Serialized)
+ {
+ If ((ECOK == One))
+ {
+ SFHK = Arg0
+ }
+ }
+
+ Method (CPUS, 1, NotSerialized)
+ {
+ If (CondRefOf (\_PR.PR00._PPC))
+ {
+ \_PR.CPPC = Arg0
+ }
+
+ If ((TCNT == 0x08))
+ {
+ Notify (\_PR.PR00, 0x80) // Performance Capability Change
+ Notify (\_PR.PR01, 0x80) // Performance Capability Change
+ Notify (\_PR.PR02, 0x80) // Performance Capability Change
+ Notify (\_PR.PR03, 0x80) // Performance Capability Change
+ Notify (\_PR.PR04, 0x80) // Performance Capability Change
+ Notify (\_PR.PR05, 0x80) // Performance Capability Change
+ Notify (\_PR.PR06, 0x80) // Performance Capability Change
+ Notify (\_PR.PR07, 0x80) // Performance Capability Change
+ }
+
+ If ((TCNT == 0x04))
+ {
+ Notify (\_PR.PR00, 0x80) // Performance Capability Change
+ Notify (\_PR.PR01, 0x80) // Performance Capability Change
+ Notify (\_PR.PR02, 0x80) // Performance Capability Change
+ Notify (\_PR.PR03, 0x80) // Performance Capability Change
+ }
+
+ If ((TCNT == 0x02))
+ {
+ Notify (\_PR.PR00, 0x80) // Performance Capability Change
+ Notify (\_PR.PR01, 0x80) // Performance Capability Change
+ }
+ Else
+ {
+ Notify (\_PR.PR00, 0x80) // Performance Capability Change
+ }
+ }
+
+ Method (ECMI, 0, NotSerialized)
+ {
+ If ((ECOK == One))
+ {
+ OSTD ()
+ CLOW = Zero
+ CMAX = (MPPP - One)
+ ACKY = FNKY /* \FNKY */
+ SASU ()
+ If ((SMA4 == One))
+ {
+ SMSZ = Zero
+ }
+ Else
+ {
+ SMSZ = One
+ }
+
+ ULID (Zero)
+ }
+ }
+
+ Method (SASU, 0, NotSerialized)
+ {
+ If ((ECOK == One))
+ {
+ If (CondRefOf (\_PR.PR00._PPC))
+ {
+ Local0 = \_PR.PR00._PPC ()
+ }
+
+ Local1 = (MPPP - One)
+ If (((SW2S == Zero) || ((SADP >= One) & (
+ SADP <= 0x02))))
+ {
+ Local0 = Zero
+ CPUS (Local0)
+ CLOW = Local0
+ }
+
+ If ((SADP == 0x03))
+ {
+ If ((Local0 < Local1))
+ {
+ Local0++
+ CPUS (Local0)
+ CLOW = Local0
+ }
+ }
+ }
+ }
+
+ Method (RPIO, 2, NotSerialized)
+ {
+ Local0 = Zero
+ If ((ECOK == One))
+ {
+ EI01 = Arg0
+ EI02 = Arg1
+ Local0 = EI03 /* \EI03 */
+ }
+
+ Return (Local0)
+ }
+
+ Method (WPIO, 3, NotSerialized)
+ {
+ If ((ECOK == One))
+ {
+ EI01 = Arg0
+ EI02 = Arg1
+ EI03 = Arg2
+ }
+ }
+
+ Method (ECMD, 3, NotSerialized)
+ {
+ If ((ECOK == One))
+ {
+ WPIO (Arg0, Arg1, Arg2)
+ While (EI03)
+ {
+ Stall (0xFF)
+ }
+
+ Local0 = RPIO (0xFB, Zero)
+ Return (Local0)
+ }
+ }
+
+ Method (CBCD, 0, NotSerialized)
+ {
+ If ((ECOK == One))
+ {
+ Local0 = MBDC /* \_SB_.PCI0.LPCB.EC0_.MBDC */
+ Local0 &= 0xE4
+ MBDC = Local0
+ }
+ }
+
+ Method (ULID, 1, NotSerialized)
+ {
+ If ((ECOK == One))
+ {
+ If ((ECLS == One))
+ {
+ Local0 = Zero
+ }
+ Else
+ {
+ Local0 = One
+ }
+
+ If (IGDS)
+ {
+ If ((Arg0 == One))
+ {
+ If ((Local0 != LIDS))
+ {
+ If (^^^GFX0.GLID (Local0))
+ {
+ If ((LIDS == Zero))
+ {
+ ^^^GFX0.CLID |= 0x80000000 /* External reference */
+ }
+
+ If ((LIDS == One))
+ {
+ ^^^GFX0.CLID |= 0x80000001 /* External reference */
+ }
+ }
+ }
+ }
+ }
+
+ LIDS = Local0
+ }
+ }
+
+ Method (OSTD, 0, NotSerialized)
+ {
+ If ((ECOK == One))
+ {
+ W7OS = Zero
+ SUSE = Zero
+ RFLG = Zero
+ If ((OSYS >= 0x07D0))
+ {
+ If ((OSYS >= 0x07D9))
+ {
+ W7OS = One
+ If ((OSKU == Zero))
+ {
+ W7OS = Zero
+ }
+ }
+ }
+ Else
+ {
+ If ((OSYS == 0x03E8))
+ {
+ RFLG = One
+ }
+
+ If ((OSYS == 0x03E9))
+ {
+ SUSE = One
+ }
+ }
+ }
+ Else
+ {
+ W7OS = Zero
+ SUSE = Zero
+ RFLG = Zero
+ }
+ }
+
+
+#include "ac.asl"
+#include "battery.asl"
+#include "kb.asl"
+#include "tpm.asl"
+}
diff --git a/src/ec/hp/it8987e/acpi/kb.asl b/src/ec/hp/it8987e/acpi/kb.asl
new file mode 100644
index 0000000..a2cf245
--- /dev/null
+++ b/src/ec/hp/it8987e/acpi/kb.asl
@@ -0,0 +1,154 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Matt Parnell <mparnell@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+// Scope is \_SB.PCI0.LPCB
+
+Device (PS2K)
+{
+ Name (_CID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _CID: Compatible ID
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0060, // Range Minimum
+ 0x0060, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0064, // Range Minimum
+ 0x0064, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IRQ (Edge, ActiveHigh, Exclusive, )
+ {1}
+ })
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ StartDependentFn (0x00, 0x00)
+ {
+ FixedIO (
+ 0x0060, // Address
+ 0x01, // Length
+ )
+ FixedIO (
+ 0x0064, // Address
+ 0x01, // Length
+ )
+ IRQNoFlags ()
+ {1}
+ }
+ EndDependentFn ()
+ })
+
+ Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
+ {
+ If (One)
+ {
+ Return (Package (0x02)
+ {
+ 0x3D,
+ 0x03
+ })
+ }
+ Else
+ {
+ Return (Package (0x02)
+ {
+ 0x1F,
+ 0x03
+ })
+ }
+ }
+
+ Method (_PSW, 1, NotSerialized) // _PSW: Power State Wake
+ {
+ KBWK = Arg0
+ }
+}
+
+Device (PS2M)
+{
+ Method (_HID, 0, NotSerialized) // _HID: Hardware ID
+ {
+ If ((CHID == 0x25))
+ {
+ Return ("*SYN326A")
+ }
+ Else
+ {
+ Return ("*SYN326A")
+ }
+ }
+
+ Method (_CID, 0, NotSerialized) // _CID: Compatible ID
+ {
+ Return (Package (0x03)
+ {
+ 0x001E2E4F,
+ 0x02002E4F,
+ 0x130FD041
+ })
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IRQ (Edge, ActiveHigh, Exclusive, )
+ {12}
+ })
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ StartDependentFn (0x00, 0x00)
+ {
+ IRQNoFlags ()
+ {12}
+ }
+ EndDependentFn ()
+ })
+ Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
+ {
+ If (One)
+ {
+ Return (Package (0x02)
+ {
+ 0x3D,
+ 0x03
+ })
+ }
+ Else
+ {
+ Return (Package (0x02)
+ {
+ 0x1F,
+ 0x03
+ })
+ }
+ }
+
+ Method (_PSW, 1, NotSerialized) // _PSW: Power State Wake
+ {
+ TPWK = Arg0
+ }
+}
diff --git a/src/ec/hp/it8987e/acpi/superio.asl b/src/ec/hp/it8987e/acpi/superio.asl
new file mode 100644
index 0000000..e912e04
--- /dev/null
+++ b/src/ec/hp/it8987e/acpi/superio.asl
@@ -0,0 +1,87 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+// Scope is \_SB.PCI0.LPCB
+
+Device (SIO)
+{
+ Name (_HID, EisaId("PNP0A05"))
+ Name (_UID, 0)
+ Name (_ADR, 0)
+
+#ifdef SIO_EC_ENABLE_PS2K
+ Device (PS2K) // Keyboard
+ {
+ Name (_UID, 0)
+ Name (_ADR, 0)
+ Name (_HID, EISAID("PNP0303"))
+ Name (_CID, EISAID("PNP030B"))
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate()
+ {
+ FixedIO (0x60, 0x01)
+ FixedIO (0x64, 0x01)
+ IRQNoFlags () {1}
+ })
+
+ Name (_PRS, ResourceTemplate()
+ {
+ StartDependentFn (0, 0)
+ {
+ FixedIO (0x60, 0x01)
+ FixedIO (0x64, 0x01)
+ IRQNoFlags () {1}
+ }
+ EndDependentFn ()
+ })
+ }
+#endif
+
+#ifdef SIO_ENABLE_PS2M
+ Device (PS2M) // Mouse
+ {
+ Name (_HID, EISAID("PNP0F13"))
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate()
+ {
+ FixedIO (0x60, 0x01)
+ FixedIO (0x64, 0x01)
+ IRQNoFlags () {12}
+ })
+
+ Name (_PRS, ResourceTemplate()
+ {
+ StartDependentFn (0, 0)
+ {
+ FixedIO (0x60, 0x01)
+ FixedIO (0x64, 0x01)
+ IRQNoFlags () {12}
+ }
+ EndDependentFn ()
+ })
+ }
+#endif
+
+}
diff --git a/src/ec/hp/it8987e/acpi/tpm.asl b/src/ec/hp/it8987e/acpi/tpm.asl
new file mode 100644
index 0000000..cb6b8a2
--- /dev/null
+++ b/src/ec/hp/it8987e/acpi/tpm.asl
@@ -0,0 +1,446 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Matt Parnell <mparnell@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device (_SB.TPM)
+{
+ Method (_HID, 0, NotSerialized) // _HID: Hardware ID
+ {
+ If (TCMF)
+ {
+ Return (0x01013469)
+ }
+ ElseIf ((TTDP == Zero))
+ {
+ Return (0x310CD041)
+ }
+ Else
+ {
+ Return ("MSFT0101")
+ }
+ }
+
+ Method (_STR, 0, NotSerialized) // _STR: Description String
+ {
+ If ((TTDP == Zero))
+ {
+ Return (Unicode ("TPM 1.2 Device"))
+ }
+ Else
+ {
+ Return (Unicode ("TPM 2.0 Device"))
+ }
+ }
+
+ Name (_UID, One) // _UID: Unique ID
+ Name (CRST, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadOnly,
+ 0x00000000, // Address Base
+ 0x00001000, // Address Length
+ _Y31)
+ Memory32Fixed (ReadOnly,
+ 0xFED70000, // Address Base
+ 0x00001000, // Address Length
+ _Y32)
+ })
+ Name (CRSD, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ 0xFED40000, // Address Base
+ 0x00005000, // Address Length
+ _Y33)
+ })
+ Name (CRSI, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ 0xFED40000, // Address Base
+ 0x00005000, // Address Length
+ _Y34)
+ })
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ If ((AMDT == One))
+ {
+ CreateDWordField (CRST, \_SB.TPM._Y31._BAS, MTFB) // _BAS: Base Address
+ CreateDWordField (CRST, \_SB.TPM._Y31._LEN, LTFB) // _LEN: Length
+ MTFB = TPMB /* \TPMB */
+ LTFB = 0x1000
+ CreateDWordField (CRST, \_SB.TPM._Y32._BAS, MTFC) // _BAS: Base Address
+ CreateDWordField (CRST, \_SB.TPM._Y32._LEN, LTFC) // _LEN: Length
+ MTFC = TPMC /* \TPMC */
+ LTFC = 0x1000
+ Return (CRST) /* \_SB_.TPM_.CRST */
+ }
+ Else
+ {
+ If ((DTPT == One))
+ {
+ CreateDWordField (CRSD, \_SB.TPM._Y33._BAS, MTFE) // _BAS: Base Address
+ CreateDWordField (CRSD, \_SB.TPM._Y33._LEN, LTFE) // _LEN: Length
+ MTFE = 0xFED40000
+ LTFE = 0x0880
+ Return (CRSD) /* \_SB_.TPM_.CRSD */
+ }
+ ElseIf ((TTPF == One))
+ {
+ CreateDWordField (CRSI, \_SB.TPM._Y34._BAS, MTFD) // _BAS: Base Address
+ CreateDWordField (CRSI, \_SB.TPM._Y34._LEN, LTFD) // _LEN: Length
+ MTFD = 0xFED40000
+ LTFD = 0x5000
+ Return (CRSI) /* \_SB_.TPM_.CRSI */
+ }
+ ElseIf ((TTPF == Zero))
+ {
+ CreateDWordField (CRSI, \_SB.TPM._Y34._BAS, MTFF) // _BAS: Base Address
+ MTFF = TPMM /* \TPMM */
+ Return (CRSI) /* \_SB_.TPM_.CRSI */
+ }
+
+ MTFE = Zero
+ LTFE = Zero
+ Return (CRSI) /* \_SB_.TPM_.CRSI */
+ }
+
+ Return (CRSI) /* \_SB_.TPM_.CRSI */
+ }
+
+ OperationRegion (TMMB, SystemMemory, 0xFED40000, 0x5000)
+ Field (TMMB, ByteAcc, Lock, Preserve)
+ {
+ Offset (0x04),
+ LCST, 32,
+ Offset (0x40),
+ CREQ, 32,
+ CSTS, 32,
+ Offset (0x4C),
+ SCMD, 32
+ }
+
+ OperationRegion (CRBD, SystemMemory, TPMM, 0x48)
+ Field (CRBD, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x04),
+ HERR, 32,
+ Offset (0x40),
+ HCMD, 32,
+ HSTS, 32
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If ((TTDP == Zero))
+ {
+ If (TPMF)
+ {
+ Return (0x0F)
+ }
+
+ Return (Zero)
+ }
+ ElseIf ((TTDP == One))
+ {
+ If (TPMF)
+ {
+ Return (0x0F)
+ }
+
+ Return (Zero)
+ }
+
+ Return (Zero)
+ }
+
+ Method (STRT, 3, Serialized)
+ {
+ OperationRegion (TPMR, SystemMemory, FTPM, 0x1000)
+ Field (TPMR, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x04),
+ FERR, 32,
+ Offset (0x0C),
+ BEGN, 32
+ }
+
+ Name (TIMR, Zero)
+ If ((ToInteger (Arg0) != Zero)){}
+ Switch (ToInteger (Arg1))
+ {
+ Case (Zero)
+ {
+ Return (Buffer (One)
+ {
+ 0x03 // .
+ })
+ }
+ Case (One)
+ {
+ TIMR = Zero
+ If ((AMDT == One))
+ {
+ While (((BEGN == One) && (TIMR < 0x0200)))
+ {
+ If ((BEGN == One))
+ {
+ Sleep (One)
+ TIMR++
+ }
+ }
+ }
+ ElseIf ((((HSTS & 0x02) | (HSTS & One)
+ ) == 0x03))
+ {
+ HCMD = One
+ }
+ Else
+ {
+ FERR = One
+ BEGN = Zero
+ }
+
+ Return (Zero)
+ }
+
+ }
+
+ Return (One)
+ }
+
+ Method (CRYF, 3, Serialized)
+ {
+ If ((ToInteger (Arg0) != One)){}
+ Switch (ToInteger (Arg1))
+ {
+ Case (Zero)
+ {
+ Return (Buffer (One)
+ {
+ 0x03 // .
+ })
+ }
+ Case (One)
+ {
+ Name (TPMV, Package (0x02)
+ {
+ One,
+ Package (0x02)
+ {
+ One,
+ 0x20
+ }
+ })
+ If ((_STA () == Zero))
+ {
+ Return (Package (0x01)
+ {
+ Zero
+ })
+ }
+
+ Return (TPMV) /* \_SB_.TPM_.CRYF.TPMV */
+ }
+
+ }
+
+ Return (Buffer (One)
+ {
+ 0x00 // .
+ })
+ }
+}
+
+
+
+Scope (_SB.TPM)
+{
+ OperationRegion (TSMI, SystemIO, SMIA, 0x02)
+ Field (TSMI, WordAcc, NoLock, Preserve)
+ {
+ SMI, 16
+ }
+
+ OperationRegion (ATNV, SystemMemory, PPIM, PPIL)
+ Field (ATNV, AnyAcc, NoLock, Preserve)
+ {
+ RQST, 32,
+ RCNT, 32,
+ ERRO, 32,
+ FLAG, 32,
+ MISC, 32,
+ OPTN, 32,
+ SRSP, 32
+ }
+
+ Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
+ {
+ If ((Arg0 == ToUUID ("3dddfaa6-361b-4eb4-a424-8d10089d1653") /* Physical Presence Interface */))
+ {
+ Switch (ToInteger (Arg2))
+ {
+ Case (Zero)
+ {
+ Return (Buffer (0x02)
+ {
+ 0xFF, 0x01 // ..
+ })
+ }
+ Case (One)
+ {
+ If ((PPIV == Zero))
+ {
+ Return ("1.2")
+ }
+ Else
+ {
+ Return ("1.3")
+ }
+ }
+ Case (0x02)
+ {
+ RQST = DerefOf (Arg3 [Zero])
+ SRSP = Zero
+ FLAG = 0x02
+ TMF1 = OFST /* \OFST */
+ SRSP = Zero
+ SMI = TMF1 /* \TMF1 */
+ Return (SRSP) /* \_SB_.TPM_.SRSP */
+ }
+ Case (0x03)
+ {
+ Name (PPI1, Package (0x02)
+ {
+ Zero,
+ Zero
+ })
+ PPI1 [One] = RQST /* \_SB_.TPM_.RQST */
+ Return (PPI1) /* \_SB_.TPM_._DSM.PPI1 */
+ }
+ Case (0x04)
+ {
+ Return (TRST) /* \TRST */
+ }
+ Case (0x05)
+ {
+ Name (PPI2, Package (0x03)
+ {
+ Zero,
+ Zero,
+ Zero
+ })
+ SRSP = Zero
+ FLAG = 0x05
+ SMI = OFST /* \OFST */
+ PPI2 [One] = RCNT /* \_SB_.TPM_.RCNT */
+ PPI2 [0x02] = ERRO /* \_SB_.TPM_.ERRO */
+ Return (PPI2) /* \_SB_.TPM_._DSM.PPI2 */
+ }
+ Case (0x06)
+ {
+ Return (0x03)
+ }
+ Case (0x07)
+ {
+ RQST = DerefOf (Arg3 [Zero])
+ FLAG = 0x07
+ OPTN = Zero
+ If ((RQST == 0x17))
+ {
+ ToInteger (DerefOf (Arg3 [One]), OPTN) /* \_SB_.TPM_.OPTN */
+ }
+
+ TMF1 = OFST /* \OFST */
+ SRSP = Zero
+ SMI = TMF1 /* \TMF1 */
+ Return (SRSP) /* \_SB_.TPM_.SRSP */
+ }
+ Case (0x08)
+ {
+ RQST = DerefOf (Arg3 [Zero])
+ FLAG = 0x08
+ TMF1 = OFST /* \OFST */
+ SRSP = Zero
+ SMI = TMF1 /* \TMF1 */
+ Return (SRSP) /* \_SB_.TPM_.SRSP */
+ }
+ Default
+ {
+ }
+
+ }
+ }
+ ElseIf ((Arg0 == ToUUID ("376054ed-cc13-4675-901c-4756d7f2d45d")))
+ {
+ Switch (ToInteger (Arg2))
+ {
+ Case (Zero)
+ {
+ Return (Buffer (One)
+ {
+ 0x03 // .
+ })
+ }
+ Case (One)
+ {
+ RQST = DerefOf (Arg3 [Zero])
+ FLAG = 0x09
+ TMF1 = OFST /* \OFST */
+ SRSP = Zero
+ SMI = TMF1 /* \TMF1 */
+ Return (SRSP) /* \_SB_.TPM_.SRSP */
+ }
+ Default
+ {
+ }
+
+ }
+ }
+
+ If ((Arg0 == ToUUID ("cf8e16a5-c1e8-4e25-b712-4f54a96702c8")))
+ {
+ Return (CRYF (Arg1, Arg2, Arg3))
+ }
+
+ If ((Arg0 == ToUUID ("6bbf6cab-5463-4714-b7cd-f0203c0368d4")))
+ {
+ Return (STRT (Arg1, Arg2, Arg3))
+ }
+
+ Return (Buffer (One)
+ {
+ 0x00 // .
+ })
+ }
+
+ Method (TPTS, 1, Serialized)
+ {
+ Switch (ToInteger (Arg0))
+ {
+ Case (0x04)
+ {
+ RQST = Zero
+ FLAG = 0x09
+ SRSP = Zero
+ SMI = OFST /* \OFST */
+ }
+ Case (0x05)
+ {
+ RQST = Zero
+ FLAG = 0x09
+ SRSP = Zero
+ SMI = OFST /* \OFST */
+ }
+
+ }
+ }
+}
diff --git a/src/ec/hp/it8987e/chip.h b/src/ec/hp/it8987e/chip.h
new file mode 100644
index 0000000..1bc9949
--- /dev/null
+++ b/src/ec/hp/it8987e/chip.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _EC_HP_IT8987E_CHIP_H
+#define _EC_HP_IT8987E_CHIP_H
+
+#include <device/device.h>
+
+struct chip_operations;
+extern struct chip_operations ec_quanta_it8987e_ops;
+
+struct ec_quanta_it8987e_config {
+};
+
+#endif /* _EC_HP_IT8987E_CHIP_H */
diff --git a/src/ec/hp/it8987e/ec.c b/src/ec/hp/it8987e/ec.c
new file mode 100644
index 0000000..db6fe3c
--- /dev/null
+++ b/src/ec/hp/it8987e/ec.c
@@ -0,0 +1,182 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <pc80/keyboard.h>
+
+#include "ec.h"
+#include "chip.h"
+
+/* helper functions from drivers/pc80/keyboard.c */
+static int input_buffer_empty(u16 status_reg)
+{
+ u32 timeout;
+ for (timeout = KBC_TIMEOUT_IN_MS; timeout && (inb(status_reg) & KBD_IBF);
+ timeout--) {
+ udelay(1000);
+ }
+
+ if (!timeout) {
+ printk(BIOS_WARNING, "EC-IT8987E Unexpected input buffer full\n");
+ printk(BIOS_WARNING, " Status (0x%x): 0x%x\n", status_reg, inb(status_reg));
+ }
+ return !!timeout;
+}
+
+
+static int output_buffer_full(u16 status_reg)
+{
+ u32 timeout;
+ for (timeout = KBC_TIMEOUT_IN_MS; timeout && ((inb(status_reg)
+ & KBD_OBF) == 0); timeout--) {
+ udelay(1000);
+ }
+
+ if (!timeout) {
+ printk(BIOS_INFO, "EC-IT8987E output buffer result timeout\n");
+ printk(BIOS_INFO, " Status (0x%x): 0x%x\n", status_reg, inb(status_reg));
+ }
+ return !!timeout;
+}
+
+
+
+/* The IT8987E 60/64 EC registers are the same command/status IB/OB KBC pair.
+ * Check status from 64 port before each command.
+ *
+ * Ex. Get panel ID command C43/D77
+ * Check IBF empty. Then Write 0x43(CMD) to 0x64 Port
+ * Check IBF empty. Then Write 0x77(DATA) to 0x60 Port
+ * Check OBF set. Then Get Data(0x03:panel ID) from 0x60
+ * Different commands return may or may not respond and may have multiple
+ * bytes. Keep it simple for nor
+ */
+
+u8 ec_kbc_read_ob(void)
+{
+ if (!output_buffer_full(KBD_STATUS)) return 0;
+ return inb(KBD_DATA);
+}
+
+void ec_kbc_write_cmd(u8 cmd)
+{
+ if (!input_buffer_empty(KBD_STATUS)) return;
+ outb(cmd, KBD_COMMAND);
+}
+
+void ec_kbc_write_ib(u8 data)
+{
+ if (!input_buffer_empty(KBD_STATUS)) return;
+ outb(data, KBD_DATA);
+}
+
+
+/*
+ * These functions are for accessing the IT8987E device RAM space via 0x66/0x68
+ */
+
+u8 ec_read_ob(void)
+{
+ if (!output_buffer_full(EC_SC)) return 0;
+ return inb(EC_DATA);
+}
+
+void ec_write_cmd(u8 cmd)
+{
+ if (!input_buffer_empty(EC_SC)) return;
+ outb(cmd, EC_SC);
+}
+
+void ec_write_ib(u8 data)
+{
+ if (!input_buffer_empty(EC_SC)) return;
+ outb(data, EC_DATA);
+}
+
+u8 ec_read(u16 addr)
+{
+ ec_write_cmd(RD_EC);
+ ec_write_ib(addr);
+ return ec_read_ob();
+}
+
+void ec_write(u16 addr, u8 data)
+{
+ ec_write_cmd(WR_EC);
+ ec_write_ib(addr);
+ ec_write_ib(data);
+}
+
+#ifndef __PRE_RAM__
+
+u8 ec_it8987e_get_event(void)
+{
+ u8 cmd = 0;
+ u8 status = inb(EC_SC);
+ if (status & SCI_EVT) {
+ ec_write_cmd(QR_EC);
+ cmd = ec_read_ob();
+ } else if (status & SMI_EVT) {
+ ec_kbc_write_cmd(EC_KBD_SMI_EVENT);
+ cmd = ec_kbc_read_ob();
+ }
+ return cmd;
+}
+
+void ec_it8987e_enable_wake_events(void)
+{
+ /*
+ * Set the bit in ECRAM that will enable the Lid switch as a wake source
+ */
+ u8 reg8 = ec_read(EC_WAKE_SRC_ENABLE);
+ ec_write(EC_WAKE_SRC_ENABLE, reg8 | EC_LID_WAKE_ENABLE);
+}
+
+#ifndef __SMM__
+static void it8987e_init(struct device *dev)
+{
+ if (!dev->enabled)
+ return;
+
+ printk(BIOS_DEBUG, "Quanta IT8987E: Initializing keyboard.\n");
+ pc_keyboard_init(NO_AUX_DEVICE);
+}
+
+static struct device_operations ops = {
+ .init = it8987e_init,
+ .read_resources = DEVICE_NOOP,
+ .enable_resources = DEVICE_NOOP,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ { NULL, 0, 0, 0, }
+};
+
+static void enable_dev(struct device *dev)
+{
+ pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations ec_quanta_it8987e_ops = {
+ CHIP_NAME("QUANTA IT8987E EC")
+ .enable_dev = enable_dev
+};
+#endif /* ! __SMM__ */
+#endif /* ! __PRE_RAM__ */
diff --git a/src/ec/hp/it8987e/ec.h b/src/ec/hp/it8987e/ec.h
new file mode 100644
index 0000000..96cb61a
--- /dev/null
+++ b/src/ec/hp/it8987e/ec.h
@@ -0,0 +1,94 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Modified by Matt Parnell <mparnell@gmail.com> to support ITL 8987E
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * EC communication interface for QUANTA IT8987E Embedded Controller.
+ */
+
+#ifndef _EC_HP_IT8987E_EC_H
+#define _EC_HP_IT8987E_EC_H
+
+#define EC_IO 0x100 /* Mainboard specific. Could be Kconfig option */
+#define EC_IO_HIGH EC_IO + 1
+#define EC_IO_LOW EC_IO + 2
+#define EC_IO_DATA EC_IO + 3
+
+/* Wait 400ms for keyboard controller ansswers */
+#define KBC_TIMEOUT_IN_MS 400
+
+// 60h/64h Command Interface
+#define KBD_DATA 0x60
+#define KBD_COMMAND 0x64
+#define KBD_STATUS 0x64
+#define KBD_IBF (1 << 1) // 1: input buffer full (data ready for ec)
+#define KBD_OBF (1 << 0) // 1: output buffer full (data ready for host)
+
+#define EC_KBD_SMI_EVENT 0xCD
+#define EC_KBD_CMD_UNMUTE 0xE8
+#define EC_KBD_CMD_MUTE 0xE9
+
+u8 ec_kbc_read_ob(void);
+void ec_kbc_write_cmd(u8 cmd);
+void ec_kbc_write_ib(u8 data);
+
+// 62h/66h Command Interface
+#define EC_DATA 0x62
+#define EC_SC 0x66 // Status & Control Register
+#define SMI_EVT (1 << 6) // 1: SMI event was triggered
+#define SCI_EVT (1 << 5) // 1: SCI event was triggered
+
+// EC Commands (defined in ec_function_spec v3.12)
+#define RD_EC 0x80
+#define WR_EC 0x81
+#define QR_EC 0x84
+
+#define EC_CMD_EXIT_BOOT_BLOCK 0x85
+#define EC_CMD_NOTIFY_ACPI_ENTER 0x86
+#define EC_CMD_NOTIFY_ACPI_EXIT 0x87
+#define EC_CMD_WARM_RESET 0x8C
+
+// ECRAM Offsets
+#define EC_PERIPH_CNTL_3 0x0D
+#define EC_USB_S3_EN 0x26
+#define EC_PERIPH_STAT_3 0x35
+#define EC_THERM_0 0x78
+#define EC_WAKE_SRC_ENABLE 0xBF
+#define EC_FW_VER 0xE8 // 2 Bytes
+#define EC_IF_MIN_VER 0xEB
+#define EC_STATUS_REG 0xEC
+#define EC_IF_MAJ_VER 0xEF
+#define EC_MBAT_STATUS 0x0138
+
+
+// EC 0.83b added status bits:
+// BIT0=EC in RO mode
+// BIT1=Recovery Key Sequence Detected
+#define EC_IN_RO_MODE 0x1
+#define EC_IN_RECOVERY_MODE 0x3
+
+// EC 0.86a added enable bit:
+#define EC_LID_WAKE_ENABLE 0x4
+
+u8 ec_read_ob(void);
+void ec_write_cmd(u8 cmd);
+void ec_write_ib(u8 data);
+
+u8 ec_read(u16 addr);
+void ec_write(u16 addr, u8 data);
+u8 ec_it8987e_get_event(void);
+void ec_it8987e_enable_wake_events(void);
+
+#endif /* _EC_HP_IT8987E_EC_H */
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