Attention is currently required from: Nico Huber, Eugene Myers, Benjamin Doron, Paul Menzel, Michael Niewöhner.
7 comments:
File src/mainboard/acer/aspire_vn7_572g/bootblock.c:
Patch Set #192, Line 18: Is a wait required?
Likely
File src/mainboard/acer/aspire_vn7_572g/devicetree.cb:
Patch Set #192, Line 14: .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
Should no longer be needed, it's the default now.
File src/mainboard/acer/aspire_vn7_572g/romstage.c:
Patch Set #192, Line 13: /* TODO: Search vendor FW for Dq/Dqs */
What does this mean? DQ/DQS mapping is only needed for LPDDR.
File src/mainboard/acer/aspire_vn7_572g/smihandler.c:
Patch Set #192, Line 23: /* Keep in sync with dsdt.asl; could insert into SSDT at runtime */
To avoid things falling out of sync, you could define this in a header and include it from dsdt.asl and here
Patch Set #192, Line 26: IDA_Disable
Where does this name come from? IDA was the name from Core 2 era processors, it's called "TURBO_MODE_DISABLE" on SKL.
Patch Set #192, Line 32: 0x1A0
Why not use the `IA32_MISC_ENABLE` macro from src/include/cpu/x86/msr.h ?
Patch Set #192, Line 54: unused_was_osys
Does this still work?
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