Arthur Heymans has uploaded this change for review.

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[WIP]soc/intel/car: Add support for bootguard CAR

Bootguard sets up CAR on its own so the only thing needed is to find a
free MTRR for our own CAR region.

Change-Id: Ifac5267f8f4b820a61519fb4a497e2ce7075cc40
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
---
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
1 file changed, 66 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/36682/1

diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
index d5f5081..3ae4829 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
@@ -23,11 +23,20 @@
 #include <rules.h>
 #include <intelblocks/msr.h>
 
+#define BOOTGUARD_MSR 0x13a
+
 .global bootblock_pre_c_entry
 bootblock_pre_c_entry:
 
 	post_code(0x20)
 
+/* Bootguard setups up it's own CAR and needs separate handling */
+check_boot_guard:
+	movl	$BOOTGUARD_MSR, %ecx
+	rdmsr
+	andl	$1, %eax
+	jnz	bootguard_car_setup
+
 	movl	$no_reset, %esp /* return address */
 	jmp	check_mtrr /* Check if CPU properly reset */
 
@@ -456,3 +465,60 @@
 
 	jmp car_init_done
 #endif
+
+bootguard_car_setup:
+	/* Configure MTRR_PHYS_MASK_HIGH for proper addressing above 4GB
+	 * based on the physical address size supported for this processor
+	 * This is based on read from CPUID EAX = 080000008h, EAX bits [7:0]
+	 */
+	movl	$0x80000008, %eax	/* Address sizes leaf */
+	cpuid
+	sub	$32, %al
+	movzx	%al, %eax
+	xorl	%esi, %esi
+	bts	%eax, %esi
+	dec	%esi			/* esi <- MTRR_PHYS_MASK_HIGH */
+
+	/* Figure put how many MTRRs we have */
+	mov	$MTRR_CAP_MSR, %ecx
+	rdmsr
+	movzb	%al, %ebx		/* Number of variable MTRRs */
+
+	/* Find a free variable MTRR */
+	movl	$MTRR_PHYS_MASK(0), %ecx
+test_is_free_mtrr:
+	rdmsr
+	test	$MTRR_PHYS_MASK_VALID, %eax
+	jz	found_free_mtrr
+	addl	$2, %ecx
+	dec	%ebx
+	jnz	test_is_free_mtrr
+
+	jmp	.halt_forever
+
+found_free_mtrr:
+	/* Assume one MTRR is enough for now */
+	decl	%ecx	/* MTRR_PHYS_BASE */
+	movl	$CONFIG_DCACHE_RAM_BASE, %eax
+	orl	$MTRR_TYPE_WRBACK, %eax
+	xorl	%edx, %edx
+	wrmsr
+
+	/* Configure the MTRR mask for the size region */
+	incl	%ecx
+	mov	$CONFIG_DCACHE_RAM_SIZE, %eax	/* size mask */
+	decl	%eax
+	not	%eax
+	or	$MTRR_PHYS_MASK_VALID, %eax
+	movl	%esi, %edx	/* edx <- MTRR_PHYS_MASK_HIGH */
+	wrmsr
+
+clear_cache_region:
+	/* Clear the cache memory region. This will also fill up the cache */
+	movl	$CONFIG_DCACHE_RAM_BASE, %edi
+	movl	$CONFIG_DCACHE_RAM_SIZE, %ecx
+	shr	$0x02, %ecx
+	xor	%eax, %eax
+	cld
+	rep	stosl
+	jmp	car_init_done

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