Patrick Rudolph has uploaded this change for review.
mb/lenovo/*: Set VR12 PSI to fix crash
When in Package C3 or deeper the PSI settings are used to switch the
CPU VR into a low power state. It was found that the voltage regulator
on the Sandy-Bridge series has non-default PSI settings, compared to
Lenovo's Ivy-Bridge series. Apply the same PSI value for PSI2 and PSI3
as the vendor BIOS does to fix a hang when the package is idle.
Since neither the vendor BIOS is open-source, nor datasheet exists for the
used VR it's unclear why those PSI values must be used and how they
influence the regulator.
The X220 already has the correct PSI values configured and is now stable
for more than 24h in Package C7 state.
Change-Id: Idf8c3719f19f7bcdab30c543215c8abd2669cfd2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
---
M src/mainboard/lenovo/l520/devicetree.cb
M src/mainboard/lenovo/t420/devicetree.cb
M src/mainboard/lenovo/t420s/devicetree.cb
M src/mainboard/lenovo/t520/devicetree.cb
4 files changed, 32 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/82070/1
diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb
index ead7e0b..a4fbe11 100644
--- a/src/mainboard/lenovo/l520/devicetree.cb
+++ b/src/mainboard/lenovo/l520/devicetree.cb
@@ -12,7 +12,14 @@
register "gpu_panel_power_up_delay" = "0"
register "gpu_pch_backlight" = "0x00000000"
register "spd_addresses" = "{0x50, 0, 0x52, 0}"
-
+ chip cpu/intel/model_206ax
+ # Values obtained from vendor BIOS
+ register "pp0_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}"
+ register "pp0_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}"
+ register "pp1_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}"
+ register "pp1_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}"
+ device cpu_cluster 0 on end
+ end
device domain 0 on
subsystemid 0x17aa 0x21dd inherit
diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb
index d4b31af..d469da6 100644
--- a/src/mainboard/lenovo/t420/devicetree.cb
+++ b/src/mainboard/lenovo/t420/devicetree.cb
@@ -16,7 +16,14 @@
register "gpu_pch_backlight" = "0x06100610"
register "spd_addresses" = "{0x50, 0, 0x51, 0}"
-
+ chip cpu/intel/model_206ax
+ # Values obtained from vendor BIOS
+ register "pp0_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}"
+ register "pp0_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}"
+ register "pp1_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}"
+ register "pp1_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}"
+ device cpu_cluster 0 on end
+ end
device domain 0 on
subsystemid 0x17aa 0x21ce inherit
diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb
index fb30917..4ce9077 100644
--- a/src/mainboard/lenovo/t420s/devicetree.cb
+++ b/src/mainboard/lenovo/t420s/devicetree.cb
@@ -16,7 +16,14 @@
register "gpu_pch_backlight" = "0x06100610"
register "spd_addresses" = "{0x50, 0, 0x51, 0}"
-
+ chip cpu/intel/model_206ax
+ # Values obtained from vendor BIOS
+ register "pp0_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}"
+ register "pp0_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}"
+ register "pp1_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}"
+ register "pp1_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}"
+ device cpu_cluster 0 on end
+ end
device domain 0 on
subsystemid 0x17aa 0x21d2 inherit
diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb
index a2e12c3..5edb63e 100644
--- a/src/mainboard/lenovo/t520/devicetree.cb
+++ b/src/mainboard/lenovo/t520/devicetree.cb
@@ -15,6 +15,14 @@
register "gpu_cpu_backlight" = "0x1155"
register "gpu_pch_backlight" = "0x06100610"
+ chip cpu/intel/model_206ax
+ # Values obtained from vendor BIOS
+ register "pp0_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}"
+ register "pp0_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}"
+ register "pp1_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}"
+ register "pp1_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}"
+ device cpu_cluster 0 on end
+ end
device domain 0 on
subsystemid 0x17aa 0x21cf inherit
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