Attention is currently required from: Nico Huber, Arthur Heymans, Patrick Rudolph.
Angel Pons would like Nico Huber, Arthur Heymans and Patrick Rudolph to review this change.
sb/intel/bd82x6x: Drop P_LVLx support in FADT
IO MWAIT redirection is not enabled, and C-states are reported using the
_CST ACPI object, which overrides the P_LVLx values.
Change-Id: I737bd58bcda3e7c5f6591e4c2309530ff035e2c8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
M src/mainboard/google/link/devicetree.cb
M src/mainboard/google/parrot/devicetree.cb
M src/mainboard/google/stout/devicetree.cb
M src/mainboard/intel/emeraldlake2/devicetree.cb
M src/mainboard/samsung/lumpy/devicetree.cb
M src/mainboard/samsung/stumpy/devicetree.cb
M src/southbridge/intel/bd82x6x/chip.h
M src/southbridge/intel/bd82x6x/fadt.c
M util/autoport/bd82x6x.go
9 files changed, 3 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/55218/1
diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb
index 33ef305..fda74da 100644
--- a/src/mainboard/google/link/devicetree.cb
+++ b/src/mainboard/google/link/devicetree.cb
@@ -58,8 +58,6 @@
# Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "1"
- register "c2_latency" = "1"
-
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb
index dbbb5cd..d748277 100644
--- a/src/mainboard/google/parrot/devicetree.cb
+++ b/src/mainboard/google/parrot/devicetree.cb
@@ -56,8 +56,6 @@
# Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "1"
- register "c2_latency" = "1"
-
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb
index 1ec596e..d1d39e5 100644
--- a/src/mainboard/google/stout/devicetree.cb
+++ b/src/mainboard/google/stout/devicetree.cb
@@ -63,8 +63,6 @@
# Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "1"
- register "c2_latency" = "1"
-
device pci 14.0 on end # USB 3.0 Controller
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb
index 80ae789..170dbaa 100644
--- a/src/mainboard/intel/emeraldlake2/devicetree.cb
+++ b/src/mainboard/intel/emeraldlake2/devicetree.cb
@@ -45,8 +45,6 @@
# SuperIO range is 0x700-0x73f
register "gen3_dec" = "0x003c0701"
- register "c2_latency" = "1"
-
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb
index 85d140c..716d1b8 100644
--- a/src/mainboard/samsung/lumpy/devicetree.cb
+++ b/src/mainboard/samsung/lumpy/devicetree.cb
@@ -56,8 +56,6 @@
register "gen2_dec" = "0x003c0b01"
register "gen3_dec" = "0x00fc1601"
- register "c2_latency" = "1"
-
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb
index 6ee21af..90ed429 100644
--- a/src/mainboard/samsung/stumpy/devicetree.cb
+++ b/src/mainboard/samsung/stumpy/devicetree.cb
@@ -38,8 +38,6 @@
register "sata_port_map" = "0x3"
- register "c2_latency" = "1"
-
register "gen1_dec" = "0x00fc1601"
# SuperIO range is 0x700-0x73f
register "gen2_dec" = "0x003c0701"
diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h
index 45f1226..6ef18fd 100644
--- a/src/southbridge/intel/bd82x6x/chip.h
+++ b/src/southbridge/intel/bd82x6x/chip.h
@@ -70,7 +70,6 @@
uint8_t pcie_aspm_f6;
uint8_t pcie_aspm_f7;
- int c2_latency;
int docking_supported;
uint8_t pcie_hotplug_map[8];
diff --git a/src/southbridge/intel/bd82x6x/fadt.c b/src/southbridge/intel/bd82x6x/fadt.c
index b0f4777..77af4e8 100644
--- a/src/southbridge/intel/bd82x6x/fadt.c
+++ b/src/southbridge/intel/bd82x6x/fadt.c
@@ -11,7 +11,6 @@
struct device *dev = pcidev_on_root(0x1f, 0);
struct southbridge_intel_bd82x6x_config *chip = dev->chip_info;
u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
- int c2_latency;
fadt->sci_int = 0x9;
@@ -32,12 +31,9 @@
fadt->pm2_cnt_len = 1;
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 16;
- c2_latency = chip->c2_latency;
- if (!c2_latency) {
- c2_latency = 101; /* c2 unsupported */
- }
- fadt->p_lvl2_lat = c2_latency;
- fadt->p_lvl3_lat = 87;
+ /* P_LVLx not used */
+ fadt->p_lvl2_lat = 101;
+ fadt->p_lvl3_lat = 1001;
/* P_CNT not supported */
fadt->duty_offset = 0;
fadt->duty_width = 0;
@@ -55,9 +51,6 @@
if (chip->docking_supported) {
fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED;
}
- if (c2_latency < 100) {
- fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED;
- }
fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm1a_evt_blk.bit_width = 32;
diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go
index e2a84e4..ad8918a 100644
--- a/util/autoport/bd82x6x.go
+++ b/util/autoport/bd82x6x.go
@@ -230,7 +230,6 @@
"sata_port_map": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0x3f),
- "c2_latency": FormatHexLE16(FADT[96:98]),
"docking_supported": (FormatBool((FADT[113] & (1 << 1)) != 0)),
"spi_uvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c8]),
"spi_lvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c4]&^(1<<23)),
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