[coreboot-gerrit] Patch set updated for coreboot: soc/intel/skylake: Add _ACx methods for TSR0 sensor for fan control

[Naresh Solanki]

Naresh Solanki ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17067

-gerrit

commit 55a7f10a78e272228b869e7884ce0fcec485d9cc
Author: Sumeet Pawnikar 
Date:   Tue Oct 18 10:57:58 2016 +0530

soc/intel/skylake: Add _ACx methods for TSR0 sensor for fan control

This patch updates below info,
    [1] Delete the DPTF_CPU_ACTIVE_AC* values because these are not
    being used. Hence, removing unnecessary defines.
    [2] Add new DPTF_TSR0_ACTIVE_AC* temperature trip points for TSR0
    external thermal sensor. These trip points are being used by _ACx
    methods to control the fan speed on Skylake-U fan based Lars and
    Kunimitsu platforms.
    [3] Follow up patches are using DPTF_CPU_ACTIVE_AC* temperature trip
    points in board specific acpi/dptf.asl (for lars, kunimitsu, etc) to
    control the fan speed as per the CPU temperature trip points.
    [4] Newly added _ACx methods for thermal sensor TSR0 in this patch
    has nothing to do with DPTF_CPU_ACTIVE_AC*.

We can control fan speed using various different thermal sensors.
    In this patch, we have added new _ACx methods for TSR0 thermal sensor.
    We run the fan at different speeds to cool down the system at different
    TSR0 temperatures.

Similarly, we considered CPU sensor temperature values and ran the fan
    at different speeds to cool down the system.

BUG=chrome-os-partner:51025
    BRANCH=firmware-glados-7820.B
    TEST=Built and booted on kunimitsu and lars EVT boards.
    Verified these _ACx methods with _ART table on these boards
    with different workloads.

Change-Id: Ia7b81e03da936c4a0f69057e43f18efd7c3b9f17
    Signed-off-by: Sumeet Pawnikar 
    Reviewed-on: https://chromium-review.googlesource.com/332368
---
 src/soc/intel/skylake/acpi/dptf/cpu.asl     | 20 ----------------
 src/soc/intel/skylake/acpi/dptf/thermal.asl | 37 +++++++++++++++++++++++++++++
 2 files changed, 37 insertions(+), 20 deletions(-)

diff --git a/src/soc/intel/skylake/acpi/dptf/cpu.asl b/src/soc/intel/skylake/acpi/dptf/cpu.asl
index 32e8863..6278b9f 100644
--- a/src/soc/intel/skylake/acpi/dptf/cpu.asl
+++ b/src/soc/intel/skylake/acpi/dptf/cpu.asl
@@ -22,26 +22,6 @@
 #define DPTF_CPU_CRITICAL       90
 #endif

-#ifndef DPTF_CPU_ACTIVE_AC0
-#define DPTF_CPU_ACTIVE_AC0     90
-#endif
-
-#ifndef DPTF_CPU_ACTIVE_AC1
-#define DPTF_CPU_ACTIVE_AC1     80
-#endif
-
-#ifndef DPTF_CPU_ACTIVE_AC2
-#define DPTF_CPU_ACTIVE_AC2     70
-#endif
-
-#ifndef DPTF_CPU_ACTIVE_AC3
-#define DPTF_CPU_ACTIVE_AC3     60
-#endif
-
-#ifndef DPTF_CPU_ACTIVE_AC4
-#define DPTF_CPU_ACTIVE_AC4     50
-#endif
-
 External (_PR.CP00._PSS, PkgObj)
 External (_PR.CP00._TSS, PkgObj)
 External (_PR.CP00._TPC, MethodObj)
diff --git a/src/soc/intel/skylake/acpi/dptf/thermal.asl b/src/soc/intel/skylake/acpi/dptf/thermal.asl
index d9bd9c0..a94c278 100644
--- a/src/soc/intel/skylake/acpi/dptf/thermal.asl
+++ b/src/soc/intel/skylake/acpi/dptf/thermal.asl
@@ -110,6 +110,43 @@ Device (TSR0)
    {
    	_SB.PCI0.LPCB.EC0.PATD (TMPI)
    }
+
+#ifdef DPTF_ENABLE_FAN_CONTROL
+	Method (_AC0)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC0))
+	}
+
+	Method (_AC1)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC1))
+	}
+
+	Method (_AC2)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC2))
+	}
+
+	Method (_AC3)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC3))
+	}
+
+	Method (_AC4)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC4))
+	}
+
+	Method (_AC5)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC5))
+	}
+
+	Method (_AC6)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC6))
+	}
+#endif
 }
 #endif