Patch Set 7:

The problem I see with this and the next patch (40963) is that it bases on the assumption that never more than one type of super i/o comfiguration enter/exit sequences can be linked in the pre-ram stages of a board. An example of a board where this assumption is not valid would be the Supermicro X10SLM+-F that only passes the build test after the two patches, because it only initializes the Nuvoton super I/O in bootblock/romstage and doesn't do anything with the ASpeed chip before ramstage.

I'd suggest adding functions in a common place with names like pnp_enter_conf_mode_55 that take pnp_devfn_t as dev parameter type instead of struct device *. Then just add the calls to the corresponding config mode enter or exit functions in the pre-ram-code.

If you look at some generated mb/static.c file, we already have PNP device nodes in romstage, and I think you can constify struct device * everywhere in pnp_enter/exit_xx declarations?

Longterm I think SIMPLE_DEVICE and pci_devfn_t and pnp_devfn_t could go away.

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: If4e742edb17ca73c01ff7b552e00e18acc6779dd
Gerrit-Change-Number: 40962
Gerrit-PatchSet: 7
Gerrit-Owner: Keith Hui <buurin@gmail.com>
Gerrit-Reviewer: Felix Held <felix-coreboot@felixheld.de>
Gerrit-Reviewer: Paul Menzel <paulepanter@users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-CC: Kyösti Mälkki <kyosti.malkki@gmail.com>
Gerrit-Comment-Date: Wed, 27 May 2020 05:16:25 +0000
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