HAOUAS Elyes (ehaouas@noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10092
-gerrit
commit 487c218fe32b8a9181f6234189bde90d5a613007 Author: Elyes HAOUAS ehaouas@noos.fr Date: Mon May 4 19:57:42 2015 +0200
ICH8: Add 82801hx RCBA registers
Change-Id: Ie1ed85d6d99ecbc0855b48beceb79e760898201b Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- src/southbridge/intel/i82801gx/i82801gx.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 4624841..9f80f50 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -200,6 +200,9 @@ int southbridge_detect_s3_resume(void); #define V1CTL 0x0020 /* 32bit */ #define V1STS 0x0026 /* 16bit */
+#define PAT 0x0030 /* 64bit */ +#define CIR1 0x0088 /* 32bit */ + #define RCTCL 0x0100 /* 32bit */ #define ESD 0x0104 /* 32bit */ #define ULD 0x0110 /* 32bit */ @@ -225,9 +228,14 @@ int southbridge_detect_s3_resume(void); #define LCTL 0x01a8 /* 16bit */ #define LSTS 0x01aa /* 16bit */
+#define CIR3 0x01fc /* 16bit */ +#define CIR4 0x0200 /* 16bit */ +#define BCR 0x0220 /* 32bit */ #define RPC 0x0224 /* 32bit */ #define RPFN 0x0238 /* 32bit */
+#define CIR5 0x1d40 /* 64bit */ + #define TRSR 0x1e00 /* 8bit */ #define TRCR 0x1e10 /* 64bit */ #define TWDR 0x1e18 /* 64bit */ @@ -237,6 +245,12 @@ int southbridge_detect_s3_resume(void); #define IOTR2 0x1e90 /* 64bit */ #define IOTR3 0x1e98 /* 64bit */
+#define DMC 0x2010 /* 32bit */ + +#define CIR6 0x2024 /* 32bit */ + +#define CIR7 0x2034 /* 32bit */ + #define TCTL 0x3000 /* 8bit */
#define D31IP 0x3100 /* 32bit */ @@ -244,11 +258,15 @@ int southbridge_detect_s3_resume(void); #define D29IP 0x3108 /* 32bit */ #define D28IP 0x310c /* 32bit */ #define D27IP 0x3110 /* 32bit */ +#define D26IP 0x3114 /* 32bit */ +#define D25IP 0x3118 /* 32bit */ #define D31IR 0x3140 /* 16bit */ #define D30IR 0x3142 /* 16bit */ #define D29IR 0x3144 /* 16bit */ #define D28IR 0x3146 /* 16bit */ #define D27IR 0x3148 /* 16bit */ +#define D26IR 0x314c /* 16bit */ +#define D25IR 0x3150 /* 16bit */ #define OIC 0x31ff /* 8bit */
#define RC 0x3400 /* 32bit */ @@ -258,6 +276,10 @@ int southbridge_detect_s3_resume(void); #define FD 0x3418 /* 32bit */ #define CG 0x341c /* 32bit */
+#define FDSW 0x3420 /* 8bit */ +#define CIR8 0x3430 /* 8bit */ +#define CIR9 0x350c /* 32bit */ + /* Function Disable (FD) register values. * Setting a bit disables the corresponding * feature.