Felix Held submitted this change.
soc/amd/phoenix/fch: only call gpp_clk_setup in FSP case
The configuration of the PCIe clock generators in the FCH was moved from
the FSP to coreboot, since all registers are documented. This
initialization is however tightly integrated in the rest of the PCIe
init code inside the reference code. In the FSP case, this code was
manually removed. openSIL will do that part of the initialization so
that there's no coreboot-specific change needed in openSIL. This will
also avoid the problems caused by mismatching configurations done by the
coreboot code and the PCIe init part of the reference code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6d64285a301ade6860c07e62dcb1a718e7a96644
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
---
M src/soc/amd/phoenix/fch.c
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/soc/amd/phoenix/fch.c b/src/soc/amd/phoenix/fch.c
index c2f0558..e9bc80a 100644
--- a/src/soc/amd/phoenix/fch.c
+++ b/src/soc/amd/phoenix/fch.c
@@ -200,7 +200,9 @@
acpi_pm_gpe_add_events_print_events();
gpio_add_events();
- gpp_clk_setup();
+ if (CONFIG(PLATFORM_USES_FSP2_0))
+ gpp_clk_setup();
+
fch_clk_output_48Mhz();
cgpll_clock_gate_init();
}
To view, visit change 80295. To unsubscribe, or for help writing mail filters, visit settings.