Subrata Banik uploaded patch set #2 to this change.
soc/intel/common: Call pci_dev_enable_bus_master() from .final ops
Enable PCI_COMMAND_MASTER for all PCI controller to ensure device can
behave as a bus master. Otherwise, the device can not generate PCI
accesses.
This patch ensures that coreboot would set PCI_COMMAND_MASTER at end of
POST to be independent of FSP supported IA-platform where FSP might clear
PCI_COMMAND_MASTER accidentally and payload won't be able to access the
PCI device resources hence leads to unnecessary delay or even timeout.
BUG=b:154900210
TEST=Able to build and boot CML and TGL platform.
Change-Id: Ife65f6029d2f966e321f616e85f59f4c37c42145
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
---
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/dsp/dsp.c
M src/soc/intel/common/block/dtt/dtt.c
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/hda/hda.c
M src/soc/intel/common/block/i2c/i2c.c
M src/soc/intel/common/block/ipu/ipu.c
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/common/block/p2sb/p2sb.c
M src/soc/intel/common/block/pcie/pcie.c
M src/soc/intel/common/block/pmc/pmc.c
M src/soc/intel/common/block/sata/sata.c
M src/soc/intel/common/block/scs/mmc.c
M src/soc/intel/common/block/scs/sd.c
M src/soc/intel/common/block/smbus/smbus.c
M src/soc/intel/common/block/spi/spi.c
M src/soc/intel/common/block/sram/sram.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/uart/uart.c
M src/soc/intel/common/block/xdci/xdci.c
M src/soc/intel/common/block/xhci/xhci.c
21 files changed, 21 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/44512/2
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