Martin Roth has uploaded this change for review.

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util/amdfwtool: Add option for setting PSP/FW shared memory location

This tells the PSP where in main memory to copy the vboot workbuf.

BUG=b:152576063
TEST=Build sharedmem destination into AMDFW, verify shared memory
gets placed at that location.

Signed-off-by: Martin Roth <martin@coreboot.org>
Original-Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Change-Id: Ie1e955e22632ca5cf146ac6eec0407091e81f519
Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2148830
Original-Reviewed-by: Simon Glass <sjg@chromium.org>
Change-Id: Id324403afa6d5a5a65ce4709be31e7f16e038da0
---
M util/amdfwtool/amdfwtool.c
1 file changed, 31 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/42044/1
diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index e6fa220..c3227b6 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -212,6 +212,8 @@
printf(" and must a multiple of 1024\n");
printf("-l | --location Location of Directory\n");
printf("-q | --anywhere Use any 64-byte aligned addr for Directory\n");
+ printf("-R | --sharedmem Location of PSP/FW shared memory\n");
+ printf("-P | --sharedmem-size Maximum size of the PSP/FW shared memory area\n");
printf("-h | --help show this help\n");
}

@@ -225,6 +227,7 @@
AMD_BIOS_UCODE = 0x66,
AMD_BIOS_APCB_BK = 0x68,
AMD_BIOS_MP2_CFG = 0x6a,
+ AMD_BIOS_PSP_SHARED_MEM = 0x6b,
AMD_BIOS_L2_PTR = 0x70,
AMD_BIOS_INVALID,
} amd_bios_type;
@@ -395,6 +398,7 @@
{ .type = AMD_BIOS_UCODE, .inst = 1, .level = BDT_LVL2 },
{ .type = AMD_BIOS_UCODE, .inst = 2, .level = BDT_LVL2 },
{ .type = AMD_BIOS_MP2_CFG, .level = BDT_LVL2 },
+ { .type = AMD_BIOS_PSP_SHARED_MEM, .inst = 0, .level = BDT_BOTH },
{ .type = AMD_BIOS_INVALID },
};

@@ -480,7 +484,7 @@
bios_directory_entry entries[];
} bios_directory_table;

-#define MAX_BIOS_ENTRIES 0x2e
+#define MAX_BIOS_ENTRIES 0x2f

typedef struct _context {
char *rom; /* target buffer, size of flash device */
@@ -864,7 +868,8 @@
fw_table[i].type != AMD_BIOS_APOB &&
fw_table[i].type != AMD_BIOS_APOB_NV &&
fw_table[i].type != AMD_BIOS_L2_PTR &&
- fw_table[i].type != AMD_BIOS_BIN))
+ fw_table[i].type != AMD_BIOS_BIN &&
+ fw_table[i].type != AMD_BIOS_PSP_SHARED_MEM))
continue;

/* BIOS Directory items may have additional requirements */
@@ -914,6 +919,11 @@
}
}

+ /* PSP_SHARED_MEM needs a destination and size */
+ if (fw_table[i].type == AMD_BIOS_PSP_SHARED_MEM &&
+ (!fw_table[i].dest || !fw_table[i].size))
+ continue;
+
biosdir->entries[count].type = fw_table[i].type;
biosdir->entries[count].region_type = fw_table[i].region_type;
biosdir->entries[count].dest = fw_table[i].dest ?
@@ -973,6 +983,11 @@

ctx->current = ALIGN(ctx->current + bytes, 0x100U);
break;
+ case AMD_BIOS_PSP_SHARED_MEM:
+ biosdir->entries[count].dest = fw_table[i].dest;
+ biosdir->entries[count].size = fw_table[i].size;
+ break;
+
default: /* everything else is copied from input */
if (fw_table[i].type == AMD_BIOS_APCB ||
fw_table[i].type == AMD_BIOS_APCB_BK)
@@ -1022,8 +1037,8 @@

fill_dir_header(biosdir, count, cookie);
}
-// Unused values: CDEPR
-static const char *optstring = "x:i:g:AMS:p:b:s:r:k:c:n:d:t:u:w:m:T:z:J:B:K:L:Y:N:UW:I:a:Q:V:e:v:j:y:G:O:X:F:H:o:f:l:hZ:q";
+// Unused values: CDE
+static const char *optstring = "x:i:g:AMS:p:b:s:r:k:c:n:d:t:u:w:m:T:z:J:B:K:L:Y:N:UW:I:a:Q:V:e:v:j:y:G:O:X:F:H:o:f:l:hZ:qR:P:";

static struct option long_options[] = {
{"xhci", required_argument, 0, 'x' },
@@ -1075,6 +1090,8 @@
{"flashsize", required_argument, 0, 'f' },
{"location", required_argument, 0, 'l' },
{"anywhere", no_argument, 0, 'q' },
+ {"sharedmem", required_argument, 0, 'R' },
+ {"sharedmem-size", required_argument, 0, 'P' },
{"help", no_argument, 0, 'h' },
{NULL, 0, 0, 0 }
};
@@ -1398,6 +1415,16 @@
case 'q':
any_location = 1;
break;
+ case 'R':
+ /* shared memory destination */
+ register_fw_addr(AMD_BIOS_PSP_SHARED_MEM, 0, optarg, 0);
+ sub = instance = 0;
+ break;
+ case 'P':
+ /* shared memory size */
+ register_fw_addr(AMD_BIOS_PSP_SHARED_MEM, NULL, NULL, optarg);
+ sub = instance = 0;
+ break;

case 'h':
usage();

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Id324403afa6d5a5a65ce4709be31e7f16e038da0
Gerrit-Change-Number: 42044
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth@google.com>
Gerrit-MessageType: newchange