soc/intel/xeon_sp/cpx: add chip operation and PCIe enumeration

Add PCIe enumeration and resource assignment/allocation.

Xeon-SP processor family has split IIO design, where PCIe domain 0 is
split into multiple stacks. Each stack has its own resource ranges (eg.
IO resource, mem32 resource, mem64 resource). The stack itself is not
PCIe device, it does not have config space to be probed/programmed.

The stack is programmed by FSP. Coreboot needs to take into account of
stack when doing PCIe enumeration and resource allocation.

Current coreboot PCIe resource allocator does not support the concept of
split IIO stack, thus entire support is done locally in this patch.

In near future, improvements will be done, first generalize for xeon-sp,
then generalize for coreboot PCIe device code.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: If461b1dc1f313d98b676dc9e91d08a1dbb9cb388
---
M src/soc/intel/xeon_sp/cpx/Makefile.inc
M src/soc/intel/xeon_sp/cpx/chip.c
M src/soc/intel/xeon_sp/cpx/chip.h
M src/soc/intel/xeon_sp/cpx/include/soc/irq.h
A src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h
A src/soc/intel/xeon_sp/cpx/soc_util.c
M src/soc/intel/xeon_sp/include/soc/util.h
7 files changed, 655 insertions(+), 12 deletions(-)