1 comment:
File src/soc/intel/cannonlake/include/soc/pci_devs.h:
Patch Set #13, Line 29: #define SA_DEVFN_PEG3 PCI_DEVFN(SA_DEV_SLOT_PEG, 3)
see Intel doc# 615211-005, section "2.2 PCI Express* Graphics Interface (PEG)"
Doesn't mention function numbers AFAICS.
for example; interestingly function 0x01 is not documented in Volume 2 (Intel doc# 615211-003).
That's 615212-003. It's easier to name things, e.g. CML DS vol2.
Also, top of the chapter it says that it's for functions 0..2.
Fspmupd.h has this:
Peg0Enable:
Offset 0x0113 - Enable/Disable PEG 0
Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise 0:Disable, 1:Enable, 2:AUTOPrimaryDisplay:
Offset 0x0177 - Selection of the primary display device
0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Switchable Graphics=> could it be, that this is the interface for external graphics, like nvidia or whatever?
??? PEG means PCIe for Graphics. Intel uses it as a pseudonym for the
PCIe lanes directly at the CPU. PEG0..2 are bifurcation options of these
16 lanes. So, yes, one can expect external graphics there. But the one I
asked about, PEG3, isn't part of it. Maybe something for the future,
Rocket Lake is said to have 4 additional lanes (for NVMe) IIRC.
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