Arthur Heymans has uploaded this change for review.
nb/intel/x4x: Don't use cached settings if CPU FSB has been changed
Using the cached CPU FSB setting can simply be wrong, in which case it won't
boot. Since the selected timings also depend on the CPU FSB, it is also best to
not use cached timings at all when a change is detected.
UNTESTED.
Change-Id: I12d91d0e892c15778409d7c00b27652ee52ca80c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
---
M src/northbridge/intel/x4x/raminit.c
1 file changed, 8 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/28506/1
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index 9d37ada..b4f103b 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -669,9 +669,16 @@
/* check SPD checksum to make sure the DIMMs haven't been
* replaced */
fast_boot = verify_spds(spd_map, ctrl_cached) == CB_SUCCESS;
- if (!fast_boot)
+ if (!fast_boot) {
printk(BIOS_DEBUG, "SPD checksums don't match,"
" dimm's have been replaced\n");
+ } else {
+ find_fsb_speed(&s);
+ fast_boot = s.max_fsb == ctrl_cached->max_fsb;
+ if (!fast_boot)
+ printk(BIOS_DEBUG,
+ "CPU FSB does match and has been replaced\n");
+ }
} else {
fast_boot = boot_path == BOOT_PATH_RESUME;
}
To view, visit change 28506. To unsubscribe, or for help writing mail filters, visit settings.