Subrata Banik would like Aamir Bohra to review this change.

View Change

soc/intel/icelake: Enable PM timer emulation support

TEST=Able to build and boot with alt/tianocore payload.

Change-Id: I7fd11e728b7a14f41f08bc39bcd92a42a8aa6cff
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
---
M src/soc/intel/icelake/cpu.c
M src/soc/intel/icelake/include/soc/cpu.h
2 files changed, 24 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/31609/1

diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c
index 0585450..f4ebacf 100644
--- a/src/soc/intel/icelake/cpu.c
+++ b/src/soc/intel/icelake/cpu.c
@@ -24,6 +24,7 @@
 #include <fsp/api.h>
 #include <intelblocks/cpulib.h>
 #include <intelblocks/mp_init.h>
+#include <intelblocks/msr.h>
 #include <intelblocks/smm.h>
 #include <romstage_handoff.h>
 #include <soc/cpu.h>
@@ -118,6 +119,23 @@
 	}
 }
 
+static void enable_pm_timer_emulation(void)
+{
+	/* ACPI PM timer emulation */
+	msr_t msr;
+	/*
+	 * The derived frequency is calculated as follows:
+	 * (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
+	 * Back solve the multiplier so the 3.579545MHz ACPI timer
+	 * frequency is used.
+	 */
+	msr.hi = (3579545ULL << 32) / CTC_FREQ;
+	/* Set PM1 timer IO port and enable*/
+	msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
+			EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
+	wrmsr(MSR_EMULATE_PM_TIMER, msr);
+}
+
 static void set_energy_perf_bias(u8 policy)
 {
 	msr_t msr;
@@ -190,6 +208,9 @@
 	/* Configure Intel Speed Shift */
 	configure_isst();
 
+	/* Enable PM timer emulation */
+	enable_pm_timer_emulation();
+
 	/* Enable Direct Cache Access */
 	configure_dca_cap();
 
diff --git a/src/soc/intel/icelake/include/soc/cpu.h b/src/soc/intel/icelake/include/soc/cpu.h
index 1e8d9e8..fae8500 100644
--- a/src/soc/intel/icelake/include/soc/cpu.h
+++ b/src/soc/intel/icelake/include/soc/cpu.h
@@ -35,6 +35,9 @@
 #define C9_POWER	0xc8
 #define C10_POWER	0xc8
 
+/* Common Timer Copy (CTC) frequency - 38.4MHz. */
+#define CTC_FREQ		38400000
+
 #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \
 	(((1 << ((base)*5)) * (limit)) / 1000)
 #define C_STATE_LATENCY_FROM_LAT_REG(reg) \

To view, visit change 31609. To unsubscribe, or for help writing mail filters, visit settings.