Maulik V Vaghela has uploaded this change for review.
mb/google/hatch: Enable PCIe WLAN and BT
Enable PCIe WLAN for hatch
1. Enable PCI Rp#13 for PCIe WLAN
2. Enable PCI clock source 3 for PCI port 13
3. GPIO pad config for WLAN and BT
USB port for BT has already been enabled so not included in this patch
BUG=b:120914069
BRANCH=none
TEST=check if code compiles correctly and verify GPIO configuration with
schematics
Change-Id: I4f2a6eb37a467ad8b8cdde8fe6b657fabb383b04
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
---
M src/mainboard/google/hatch/variants/baseboard/devicetree.cb
M src/mainboard/google/hatch/variants/baseboard/gpio.c
2 files changed, 22 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/30467/1
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index 0e80ab3..1ad5589 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -49,7 +49,6 @@
register "SataPortsDevSlp[1]" = "1"
register "satapwroptimize" = "1"
-
# Enable Root port 9(x4) for NVMe.
register "PcieRpEnable[8]" = "1"
# RP 9 uses CLK SRC 1
@@ -57,6 +56,12 @@
# ClkReq-to-ClkSrc mapping for CLK SRC 1
register "PcieClkSrcClkReq[1]" = "1"
+ # PCIe port 13 for M.2 E-key WLAN
+ register "PcieRpEnable[13]" = "1"
+ # RP 13 uses CLK SRC 3
+ register "PcieClkSrcUsage[3]" = "13"
+ register "PcieClkSrcClkReq[3]" = "3"
+
device domain 0 on
device pci 00.0 off end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
@@ -119,7 +124,12 @@
device pci 1d.1 off end # PCI Express Port 10
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12
- device pci 1d.4 off end # PCI Express Port 13 (x4)
+ device pci 1d.4 on
+ chip drivers/intel/wifi
+ register "wake" = "GPE0_DW1_01"
+ device pci 00.0 on end
+ end
+ end # PCI Express Port 13 (x4)
device pci 1e.0 on end # UART #0
device pci 1e.1 off end # UART #1
device pci 1e.2 on
diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c
index ce78bb5..4a6341f 100644
--- a/src/mainboard/google/hatch/variants/baseboard/gpio.c
+++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c
@@ -23,6 +23,8 @@
PAD_CFG_GPI_APIC(GPP_A21, NONE, PLTRST, LEVEL, INVERT),
/* SRCCLKREQ1 */
PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
+ /* PCIE_14_WLAN_CLKREQ_ODL */
+ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
/* H1_SLAVE_SPI_CS_L */
PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
/* H1_SLAVE_SPI_CLK */
@@ -31,12 +33,16 @@
PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
/* H1_SLAVE_SPI_MOSI_R */
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+ /* PCIE_14_WLAN_WAKE_ODL */
+ PAD_CFG_GPI(GPP_C1, NONE, PLTRST),
/* TOUCHSCREEN_DIS_L */
PAD_CFG_GPO(GPP_C4, 1, DEEP),
/* GPP_C10_TP */
PAD_NC(GPP_C10, DN_20K),
/* GPP_C11_TP */
PAD_NC(GPP_C11, DN_20K),
+ /* BT_DISABLE_L */
+ PAD_CFG_GPO(GPP_C14, 1, DEEP),
/* PCH_I2C_TRACKPAD_SDA */
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
/* PCH_I2C_TRACKPAD_SCL */
@@ -45,12 +51,14 @@
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
/* PCH_I2C_TOUCHSCREEN_SCL */
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
- /* H1_PCH_INT_ODL */
- PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, INVERT),
/* PCH_WP_OD */
PAD_CFG_GPI(GPP_C20, NONE, DEEP),
+ /* H1_PCH_INT_ODL */
+ PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, INVERT),
/* EC_IN_RW_OD */
PAD_CFG_GPI(GPP_C22, NONE, DEEP),
+ /* WLAN_PE_RST# */
+ PAD_CFG_GPO(GPP_C23, 1, DEEP),
/* TOUCHSCREEN_RST_L */
PAD_CFG_GPO(GPP_D15, 1, DEEP),
/* TOUCHSCREEN_INT_L */
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