Peter Lemenkov has uploaded this change for review.
mb/lenovo/t420(s): whitespace and cosmetic
Change-Id: I53bdd90ae47b52dfdfec27229c6b904487fa2081
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
---
M src/mainboard/lenovo/t420/cmos.layout
M src/mainboard/lenovo/t420s/Kconfig
M src/mainboard/lenovo/t420s/devicetree.cb
M src/mainboard/lenovo/t420s/early_init.c
M src/mainboard/lenovo/t420s/gpio.c
M src/mainboard/lenovo/t420s/smihandler.c
6 files changed, 13 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/40380/1
diff --git a/src/mainboard/lenovo/t420/cmos.layout b/src/mainboard/lenovo/t420/cmos.layout
index f9b75f2..26e6300 100644
--- a/src/mainboard/lenovo/t420/cmos.layout
+++ b/src/mainboard/lenovo/t420/cmos.layout
@@ -74,8 +74,8 @@
# coreboot config options: northbridge
432 3 e 11 gfx_uma_size
-435 2 e 12 hybrid_graphics_mode
-#437 3 r 0 unused
+435 2 e 12 hybrid_graphics_mode
+#437 3 r 0 unused
440 8 h 0 volume
diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig
index f29d50f..e2fd824 100644
--- a/src/mainboard/lenovo/t420s/Kconfig
+++ b/src/mainboard/lenovo/t420s/Kconfig
@@ -16,10 +16,10 @@
select HAVE_CMOS_DEFAULT
select HAVE_ACPI_RESUME
select INTEL_INT15
- select MAINBOARD_HAS_LIBGFXINIT
- select GFX_GMA_PANEL_1_ON_LVDS
select MAINBOARD_HAS_LPC_TPM
select MAINBOARD_HAS_TPM1
+ select MAINBOARD_HAS_LIBGFXINIT
+ select GFX_GMA_PANEL_1_ON_LVDS
select DRIVERS_LENOVO_HYBRID_GRAPHICS
select INTEL_GMA_HAVE_VBT
select MAINBOARD_USES_IFD_GBE_REGION
diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb
index 1f794c1..b3399c3 100644
--- a/src/mainboard/lenovo/t420s/devicetree.cb
+++ b/src/mainboard/lenovo/t420s/devicetree.cb
@@ -1,4 +1,5 @@
chip northbridge/intel/sandybridge
+ # IGD Displays
register "gfx" = "GMA_STATIC_DISPLAYS(1)"
# Enable DisplayPort Hotplug with 6ms pulse
@@ -66,6 +67,7 @@
register "c2_latency" = "101" # c2 not supported
+ # device specific SPI configuration
register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005"
diff --git a/src/mainboard/lenovo/t420s/early_init.c b/src/mainboard/lenovo/t420s/early_init.c
index 212be38..4f5f69d 100644
--- a/src/mainboard/lenovo/t420s/early_init.c
+++ b/src/mainboard/lenovo/t420s/early_init.c
@@ -35,8 +35,8 @@
}
const struct southbridge_usb_port mainboard_usb_ports[] = {
- { 0, 1, -1 }, /* P0 empty */
- { 1, 1, 1 }, /* P1 system port 2 (To system port) (EHCI debug), OC 1 */
+ { 0, 1, -1 }, /* P0: empty */
+ { 1, 1, 1 }, /* P1: system port 2 (To system port) (EHCI debug), OC 1 */
{ 1, 1, -1 }, /* P2: HALF MINICARD (WLAN) no oc */
{ 1, 0, -1 }, /* P3: WWAN, no OC */
{ 1, 1, -1 }, /* P4: smartcard, no OC */
diff --git a/src/mainboard/lenovo/t420s/gpio.c b/src/mainboard/lenovo/t420s/gpio.c
index 0b64efe..daca020 100644
--- a/src/mainboard/lenovo/t420s/gpio.c
+++ b/src/mainboard/lenovo/t420s/gpio.c
@@ -2,6 +2,7 @@
/* This file is part of the coreboot project. */
#include <southbridge/intel/common/gpio.h>
+
static const struct pch_gpio_set1 pch_gpio_set1_mode = {
.gpio0 = GPIO_MODE_GPIO, // -USB30_SMIB - input
.gpio1 = GPIO_MODE_GPIO, // -EC_SCI - input
@@ -69,7 +70,7 @@
.gpio28 = GPIO_DIR_OUTPUT,
.gpio29 = GPIO_DIR_OUTPUT,
.gpio30 = GPIO_DIR_OUTPUT,
- .gpio31 = GPIO_DIR_INPUT
+ .gpio31 = GPIO_DIR_INPUT,
};
static const struct pch_gpio_set1 pch_gpio_set1_level = {
@@ -108,8 +109,8 @@
};
static const struct pch_gpio_set1 pch_gpio_set1_invert = {
- .gpio0 = GPIO_INVERT,
- .gpio1 = GPIO_INVERT,
+ .gpio0 = GPIO_INVERT,
+ .gpio1 = GPIO_INVERT,
.gpio13 = GPIO_INVERT,
};
diff --git a/src/mainboard/lenovo/t420s/smihandler.c b/src/mainboard/lenovo/t420s/smihandler.c
index 84b9c3a..4432995 100644
--- a/src/mainboard/lenovo/t420s/smihandler.c
+++ b/src/mainboard/lenovo/t420s/smihandler.c
@@ -6,8 +6,8 @@
#include <cpu/x86/smm.h>
#include <ec/acpi/ec.h>
#include <ec/lenovo/h8/h8.h>
-#include <southbridge/intel/common/pmutil.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/pmutil.h>
#define GPE_EC_SCI 1
#define GPE_EC_WAKE 13
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