Jonathan Zhang would like Anjaneya "Reddy" Chagam to review this change.
vendorcode/intel/fsp/fsp2_0: Add FSP header files for Skylake-SP
Add header files for FSP of Skylake Scalable Processor.
These header files are from an Intel engineering build.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Tested-by: johnny_lin@wiwynn.com
Change-Id: If47f102c2c7979da1196f8c6b315d5be558e786c
---
A src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspUpd.h
A src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h
A src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspsUpd.h
A src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FsptUpd.h
A src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_iiouds.h
A src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_memmap.h
6 files changed, 1,264 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/39108/1
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspUpd.h
new file mode 100644
index 0000000..daa0bb4
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspUpd.h
@@ -0,0 +1,48 @@
+/** @file
+
+Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPUPD_H__
+#define __FSPUPD_H__
+
+#include <FspEas.h>
+
+#pragma pack(1)
+
+#define FSPT_UPD_SIGNATURE 0x545F4450554C4E41 /* 'ANLUPD_T' */
+
+#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4E41 /* 'ANLUPD_M' */
+
+#define FSPS_UPD_SIGNATURE 0x535F4450554C4E41 /* 'ANLUPD_S' */
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h
new file mode 100644
index 0000000..80ca157
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h
@@ -0,0 +1,545 @@
+/** @file
+
+Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPMUPD_H__
+#define __FSPMUPD_H__
+
+#include <FspUpd.h>
+
+#pragma pack(1)
+
+/**
+ FSP Header Version Number
+**/
+#define FSP_UPD_VERSION (0x1947)
+
+#define MAX_CHANNEL 6 /* Maximum Number of Memory Channels */
+#define MAX_DIMM 2 /* Maximum Number of DIMMs per Channel */
+
+/**
+ IIO PCIe Ports
+ **/
+typedef enum {
+ PORT_0 = 0,
+ // IOU2
+ PORT_1A,
+ PORT_1B,
+ PORT_1C,
+ PORT_1D,
+ // IOU0
+ PORT_2A,
+ PORT_2B,
+ PORT_2C,
+ PORT_2D,
+ // IOU1
+ PORT_3A,
+ PORT_3B,
+ PORT_3C,
+ PORT_3D,
+ // MCP0
+ PORT_4A,
+ PORT_4B,
+ PORT_4C,
+ PORT_4D,
+ // MCP1
+ PORT_5A,
+ PORT_5B,
+ PORT_5C,
+ PORT_5D,
+ MAX_PORTS
+} PCIE_PORTS;
+
+/**
+ IIO Stacks
+ **/
+typedef enum {
+ CSTACK = 0,
+ PSTACK0,
+ PSTACK1,
+ PSTACK2,
+ PSTACK3,
+ PSTACK4,
+ MAX_STACKS
+} IIO_STACKS;
+
+/**
+ NTB Per Port Definition
+ **/
+typedef enum {
+ NTB_PORT_TRANSPARENT = 0,
+ NTB_PORT_NTB_NTB
+} NTB_PPD;
+
+/**
+ NTB Upstream/Downstream Configuration
+ **/
+typedef enum {
+ NTB_XLINK_DSD_USP = 2,
+ NTB_XLINK_USD_DSP
+} NTB_XLINK;
+
+/**
+ PCIe Link Speed Selection
+ **/
+typedef enum {
+ PcieAuto = 0,
+ PcieGen1,
+ PcieGen2,
+ PcieGen3
+} PCIE_LINK_SPEED;
+
+/**
+ GPIO Pad Number
+**/
+
+typedef UINT32 UPD_GPIO_PAD;
+
+/**
+ UPD_GPIO_CONFIG:
+ 64 bit struct defining GPIO PAD configuration
+**/
+typedef struct {
+ /**
+ Pad Mode
+ Pad can be set as GPIO or one of its native functions.
+ When in native mode setting Direction (except Inversion), OutputState,
+ InterruptConfig and Host Software Pad Ownership are unnecessary.
+ Refer to definition of GPIO_PAD_MODE.
+ Refer to EDS for each native mode according to the pad.
+ **/
+ UINT32 PadMode : 4;
+ /**
+ Host Software Pad Ownership
+ Set pad to ACPI mode or GPIO Driver Mode.
+ Refer to definition of GPIO_HOSTSW_OWN.
+ **/
+ UINT32 HostSoftPadOwn : 2;
+ /**
+ GPIO Direction
+ Can choose between In, In with inversion Out, both In and Out,
+ both In with inversion and out or disabling both.
+ Refer to definition of GPIO_DIRECTION for supported settings.
+ **/
+ UINT32 Direction : 5;
+ /**
+ Output State
+ Set Pad output value.
+ Refer to definition of GPIO_OUTPUT_STATE for supported settings.
+ This setting takes place when output is enabled.
+ **/
+ UINT32 OutputState : 2;
+ /**
+ GPIO Interrupt Configuration
+ Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). This setting
+ is applicable only if GPIO is in input mode.
+ If GPIO is set to cause an SCI then also Gpe is enabled for this pad.
+ Refer to definition of GPIO_INT_CONFIG for supported settings.
+ **/
+ UINT32 InterruptConfig : 8;
+ /**
+ GPIO Power Configuration.
+ This setting controls Pad Reset Configuration.
+ Refer to definition of GPIO_RESET_CONFIG for supported settings.
+ **/
+ UINT32 PowerConfig : 4;
+
+ /**
+ GPIO Electrical Configuration
+ This setting controls pads termination and voltage tolerance.
+ Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings.
+ **/
+ UINT32 ElectricalConfig : 7;
+
+ /**
+ GPIO Lock Configuration
+ This setting controls pads lock.
+ Refer to definition of GPIO_LOCK_CONFIG for supported settings.
+ **/
+ UINT32 LockConfig : 3;
+ /**
+ Additional GPIO configuration
+ Refer to definition of GPIO_OTHER_CONFIG for supported settings.
+ **/
+ UINT32 OtherSettings : 2;
+
+ UINT32 RsvdBits : 27; ///< Reserved bits for future extension
+
+ UINT32 RsvdBits1; ///< Reserved bits for future extension
+} UPD_GPIO_CONFIG;
+
+/**
+ UPD_GPIO_INIT_CONFIG:
+ Defines a GPIO Pad and its respective configuration
+ Constitutes one entry in the GPIO config table
+ Reference FSP implementation:
+ AndersonLakePlatPkg\Uba\UbaMain\Pei\TypeAndersonCreek\GpioTable.c
+ Bootloaders can include the following to define GPIO PADs/other macros:
+ PurleySktPkg\SouthClusterLbg\Include\Library\GpioLib.h
+**/
+typedef struct {
+ UPD_GPIO_PAD GpioPad;
+ UPD_GPIO_CONFIG GpioConfig;
+} UPD_GPIO_INIT_CONFIG;
+
+/**
+ GPIOTABLE_CONFIG:
+ GpioTable - Base Address of the Gpio Table declared by the
+ bootloader.
+ Default: NULL
+ NumberofEntries - Number of Entries in the GPIO Table provided
+ Default: 0
+ If GpioTable is Null or NumberofEntries is 0, then FSP will handle Gpio Pad
+ configuration using default GPIO_INIT_CONFIG tables
+**/
+typedef struct {
+ UPD_GPIO_INIT_CONFIG *GpioTable;
+ UINT32 NumberOfEntries;
+} GPIOTABLE_CONFIG;
+
+/**
+ UPD_IIO_BIFURCATION_DATA_ENTRY:
+ Defines IIO Bifurcation for IIO Units
+ Constitutes one entry in the IIO Bifurcation table, describing bifurcation entries as:
+ Socket | IOU | Bifurcation
+ Valid IouNumbers are from 0 to 4
+ Reference FSP Implementation :
+ AndersonLakePlatPkg\Uba\UbaMain\Pei\TypeAndersonCreek\IioBifurInit.c
+ Definitions for relevant bifurcation macros:
+ NumberCpRcPkg\Library\BaseMemoryCoreLib\Chip\Skx\Include\Iio\IioRegs.h
+**/
+typedef struct {
+ UINT8 Socket;
+ UINT8 IouNumber;
+ UINT8 Bifurcation;
+} UPD_IIO_BIFURCATION_DATA_ENTRY;
+
+/**
+ IIOBIFURCATION_CONFIG:
+ IIoBifurcationTable - Base Address of the IIO Bifurcation table
+ declared by the bootloader
+ Default: NULL
+ NumberofEntries - Number of Entries in the IIO Bifurcation Table
+ Default: 0
+ If IIoBifurcationTable is Null or NumberofEntries is 0, then FSP will handle IIO
+ bifurcation using default IIO_BIFURCATION_DATA_ENTRY tables
+**/
+typedef struct {
+ UPD_IIO_BIFURCATION_DATA_ENTRY *IIoBifurcationTable;
+ UINT32 NumberOfEntries;
+} IIOBIFURCATION_CONFIG;
+
+/**
+ VTD_CONFIG :
+ VT direct IO Configuration Support
+ VTdSupport - Enable/Disable VTd Support
+ CoherencySupport - Enable/Disable Coherency Support
+ ATS - Enable/Disable Address Translation Services
+ FSP Will Disable VTd by default
+**/
+typedef struct {
+ UINT8 VTdSupport;
+ UINT8 CoherencySupport;
+ UINT8 ATS;
+} VTD_CONFIG;
+
+/**
+ UPD_PCIE_PORT_CONFIG
+ PCIe port configuration
+ PortIndex - Index of the port to be configured as defined by PCI_PORTS
+ HidePort - Hide the selected port
+ DeEmphasis - DeEmphasis of the selected PCIe port
+ PortLinkSpeed - Port Link Speed. Use PCIE_LINK_SPEED to set
+ DfxDnTxPreset - PCIe Downstream Tx Preset, valid values (0x00 - 0x09,
+ 0xFF is Auto, Auto sets 0x07)
+ DfxRxPreset - PCIe Downstream Rx Preset, valid values (0x00 - 0x06, 0xFF is Auto)
+ DfxUpTxPreset - PCIe Upstream Tx Preset, valid values (0x00 - 0x09, 0xFF is Auto)
+ Sris - Enable/Disable SRIS (0x00 - Disable, 0x01 - Enable)
+ PcieCommonClock - Configure port clocking. (0x00 - Distinct, 0x01 - Common)
+ MaxPayload - PCIe Max Payload Size on the port
+ NtbPpd - NTB port Configuration as defined in NTB_PPD
+ NtbSplitBar - 0: Use one 64, 1: Use two 32-bit split bars
+ NtbSBar01Prefetch - Configure Split BAR 0/1 as prefetchable
+ NtbXlinkCtlOverride - NTB Cross-link as defined in NTB_XLINK
+ NtbBarSizePBar4 - Set Prefetchable BAR 4 size for the primary NTB side in case
+ Split Bar is Enabled
+ NtbBarSizePBar5 - Set Prefetchable BAR 5 size for the primary NTB side in case
+ Split Bar is Enabled
+ FSP_WA: Till FSP fixes NtbBarSizeOverride, parameters below are MANDATORY!:
+ These BAR size registers are write once registers and will be programmed with 0
+ if not passed as FSP is
+ hardcoding NtbBarSizeOverride to 0x01 for now.
+ Split BAR sizes would need to be programmed mandatorily as well in case split bars
+ are enabled.
+ NtbBarSizePBar23 - Set Prefetchable BAR 23 size for the primary NTB side
+ NtbBarSizePBar45 - Used to set bar 4 and 5 sizes in case Split Bar is Disabled
+ NtbBarSizeSBar23 - Set Prefetchable BAR 23 size for the secondary NTB side
+ NtbBarSizeSBar45 - Set Prefetchable BAR 45 size for the secondary NTB side in case
+ Split Bar is disabled
+**/
+typedef struct {
+ UINT32 PortIndex;
+ UINT8 HidePort;
+ UINT8 DeEmphasis;
+ UINT8 PortLinkSpeed;
+ UINT8 MaxPayload;
+ UINT8 DfxDnTxPreset;
+ UINT8 DfxRxPreset;
+ UINT8 DfxUpTxPreset;
+ UINT8 Sris;
+ UINT8 PcieCommonClock;
+ UINT8 NtbPpd;
+ UINT8 NtbSplitBar;
+ UINT8 NtbBarSizePBar23;
+ UINT8 NtbBarSizePBar4;
+ UINT8 NtbBarSizePBar5;
+ UINT8 NtbBarSizePBar45;
+ UINT8 NtbBarSizeSBar23;
+ UINT8 NtbBarSizeSBar4;
+ UINT8 NtbBarSizeSBar5;
+ UINT8 NtbBarSizeSBar45;
+ UINT8 NtbSBar01Prefetch;
+ UINT8 NtbXlinkCtlOverride;
+} UPD_PCI_PORT_CONFIG;
+
+/**
+ PCIEPORT_CONFIG:
+ PciePortConfiguration - Pointer to an array of PCIe port configuration structures
+ as declared above
+ NumberOfEntries - Number of elements in the PciePortConfiguration Array
+**/
+typedef struct {
+ UPD_PCI_PORT_CONFIG *ConfigurationTable;
+
+ UINT16 NumberOfEntries;
+} IIOPCIPORT_CONFIG;
+
+/**
+ UPD_IIO_STACK_RESOURCE_CONFIG:
+ StackIndex - Index of the CPU IIO Stack to be configured as defined by IIO_STACKS
+ PciResourceIoBase
+ PciResourceIoLimit
+ PciResourceMem32Base
+ PciResourceMem32Limit
+ PciResourceMem64Base
+ PciResourceMem64Limit
+**/
+typedef struct {
+ UINT8 StackIndex;
+ UINT16 PciResourceIoBase;
+ UINT16 PciResourceIoLimit;
+ UINT32 PciResourceMem32Base;
+ UINT32 PciResourceMem32Limit;
+ UINT64 PciResourceMem64Base;
+ UINT64 PciResourceMem64Limit;
+} UPD_IIO_STACK_RESOURCE_CONFIG;
+
+/**
+ IIORESOURCE_CONFIG:
+ ResourceConfigTable - Pointer to an Iio Stack Resource Configuration Structure Array
+ NumberOfEntries - Number of Entries in the Iio Stack Resource Configuration Array
+**/
+typedef struct {
+ UPD_IIO_STACK_RESOURCE_CONFIG *ResourceTable;
+ UINT16 NumberOfEntries;
+} IIORESOURCE_CONFIG;
+
+/**
+ UPD_PCH_PCIE_PORT:
+ PortIndex - PCH PCIe Port Index.
+ Valid Port Numbers are: 0 to 19.
+ Enable - Enable/Disable PCH PCIe port
+ PortLinkSpeed - Port Link Speed. Use PCIE_LINK_SPEED to set
+**/
+typedef struct {
+ UINT8 PortIndex;
+ UINT8 ForceEnable;
+ UINT8 PortLinkSpeed;
+} UPD_PCH_PCIE_PORT;
+
+/**
+ PCHPCIPORT_CONFIG:
+ PciPortConfig - Pointer to an array of PCH PCI Ports to be configured
+ RootPortFunctionSwapping - Disable root port swapping based on device
+ connection status
+ PciePllSsc - Specifies the Pcie Pll Spread Spectrum Percentage
+ The value of this policy is in 1/10th percent units.
+ Valid spread range: 0-20. Auto: 0xFE (sets it to hardware default)
+ Completely Disable PCIe PLL SSC: 0xFF
+ A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0%
+ NumberOfEntries - Number of entries in the PCH PCI Port configuration
+**/
+typedef struct {
+ UPD_PCH_PCIE_PORT *PciPortConfig;
+ UINT8 RootPortFunctionSwapping;
+ UINT8 PciePllSsc;
+ UINT16 NumberOfEntries;
+} PCHPCIPORT_CONFIG;
+
+/** FSP-M Configuration
+**/
+typedef struct {
+
+/** Offset 0x0040 - MRC Debug Print Level
+ Select the FSP MRC debug message print level. Options are a bitmask, so you can
+ combine options. BIT0:MIN DEBUG, BIT1:MAX DEBUG, BIT2:TRACE, BIT3:MEM TRAIN, BIT4:TEST,
+ BIT5:CPGC, BIT6:REG ACCESS
+**/
+ UINT8 PcdFspMrcDebugPrintErrorLevel;
+
+/** Offset 0x0041 - KTI Debug Print Level
+ Select the FSP KTI debug message print level. Options are a bitmask, so you can
+ combine options. BIT0:ERROR, BIT1:WARNING, BIT2:INFO0, BIT3:INFO1
+**/
+ UINT8 PcdFspKtiDebugPrintErrorLevel;
+
+/** Offset 0x0042 - HSUART Device
+ Select the PCI High Speed UART Device for Serial Port.
+ 0:HSUART0, 1:HSUART1, 2:HSUART2
+**/
+ UINT8 PcdHsuartDevice;
+
+/** Offset 0x0043 - Customer Revision
+ The Customer can set this revision string for their own purpose.
+**/
+ UINT8 PcdCustomerRevision[32];
+
+/** Offset 0x0063 - GpioConfig
+ GpioConfig Struct. Defaults: GpioTable:NULL, NumberOfEntries:0x00
+**/
+ GPIOTABLE_CONFIG GpioConfig;
+
+/** Offset 0x006B - IioBifurcationConfig
+ IioBifurcationConfig Table Struct. Defaults: IioBifurcationTable:NULL,
+ NumberOfEntries:0x00
+**/
+ IIOBIFURCATION_CONFIG IioBifurcationConfig;
+
+/** Offset 0x0073
+**/
+ UINT8 UnusedUpdSpace0[16];
+
+/** Offset 0x0083 - VTdConfig
+ VTdConfig Struct. Defaults: All values are set to 0. VTd Disabled.
+**/
+ VTD_CONFIG VTdConfig;
+
+ UINT8 reserved1[35];
+
+/** Offset 0x00A9 - Board ID Number
+ Select the BoardId based on the target Platform. Default assumes an unknown board.
+**/
+ UINT8 BoardId;
+
+ UINT8 reserved2[24];
+
+/** Offset 0x00C2 **/
+ VOID *SetupStructPtr;
+
+ UINT8 reserved3[20];
+
+/** Offset 0x00DA - IioPciConfig
+ IIO Pci Port Config Struct. Defaults: All pointers are NULL. All values are set to zero.
+**/
+ IIOPCIPORT_CONFIG IioPciConfig;
+
+/** Offset 0x00E0 - PchPciConfig
+ PCH Pci Port Config Struct. Defaults: All pointers are NULL. All values are set to zero.
+**/
+ PCHPCIPORT_CONFIG PchPciConfig;
+
+/** Offset 0x00E8 - IioResourceConfig
+ IIO Resource Struct. Defaults: All pointers are NULL. All values are set to zero.
+**/
+ IIORESOURCE_CONFIG IioResourceConfig;
+
+ UINT8 reserved4[3];
+
+/** Offset 0x00F1 - DCI Enable
+ Enable / Disable DCI
+ $EN_DIS
+**/
+ UINT8 PchDciEn;
+
+/** Offset 0x00F2 - IO Margining Tool (IOMT) Enable
+ Enable / Disable Io Margining Tool
+ $EN_DIS
+**/
+ UINT8 IomtEnable;
+
+/** Offset 0x00F3 - Hyper Threading (HT) disable
+ Disable Hyper threading. Disable: 0x01 | Enable: 0x00 | Default - HT enabled
+ $EN_DIS
+**/
+ UINT8 HyperThreadingDisable;
+
+/** Offset 0x00F4
+**/
+ UINT8 UnusedUpdSpace1[236];
+
+/** Offset 0x01E0
+**/
+ UINT8 ReservedMemoryInitUpd[16];
+} FSP_M_CONFIG;
+
+/** Fsp M UPD Configuration
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+ FSP_UPD_HEADER FspUpdHeader;
+
+/** Offset 0x0020
+**/
+ FSPM_ARCH_UPD FspmArchUpd;
+
+/** Offset 0x0040
+**/
+ FSP_M_CONFIG FspmConfig;
+
+/** Offset 0x01F0 - FspmVersion
+ FSP-M UPD Version Number
+**/
+ UINT16 FspmUpdVersion;
+
+/** Offset 0x01F2
+**/
+ UINT8 UnusedUpdSpace2[12];
+
+/** Offset 0x01FE
+**/
+ UINT16 UpdTerminator;
+} FSPM_UPD;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspsUpd.h
new file mode 100644
index 0000000..b93a1af
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspsUpd.h
@@ -0,0 +1,198 @@
+/** @file
+
+Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPSUPD_H__
+#define __FSPSUPD_H__
+
+#include <FspUpd.h>
+
+#pragma pack(1)
+
+
+/** FSP-S Configuration
+**/
+typedef struct {
+
+/** Offset 0x0020 - PCIe Controller 0 Bifurcation
+ Configure PCI Express controller 0 bifurcation.
+ 0:X2X2X2X2, 1:X2X2X4, 2:X4X2X2, 3:X4X4, 4:X8
+**/
+ UINT8 PcdBifurcationPcie0;
+
+/** Offset 0x0021 - PCIe Controller 1 Bifurcation
+ Configure PCI Express controller 1 bifurcation.
+ 0:X2X2X2X2, 1:X2X2X4, 2:X4X2X2, 3:X4X4, 4:X8
+**/
+ UINT8 PcdBifurcationPcie1;
+
+/** Offset 0x0022 - Active Core Count
+ Select # of Active Cores (Default: 0, 0:ALL, 1..15 = 1..15 Cores)
+ 0:ALL, 1:1, 2:2, 3:3, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13,
+ 14:14, 15:15
+**/
+ UINT8 PcdActiveCoreCount;
+
+/** Offset 0x0023
+**/
+ UINT32 PcdCpuMicrocodePatchBase;
+
+/** Offset 0x0027
+**/
+ UINT32 PcdCpuMicrocodePatchSize;
+
+/** Offset 0x002B - PCIe Controller 0
+ Enable / Disable PCI Express controller 0
+ $EN_DIS
+**/
+ UINT8 PcdEnablePcie0;
+
+/** Offset 0x002C - PCIe Controller 1
+ Enable / Disable PCI Express controller 1
+ $EN_DIS
+**/
+ UINT8 PcdEnablePcie1;
+
+/** Offset 0x002D - Embedded Multi-Media Controller (eMMC)
+ Enable / Disable Embedded Multi-Media controller
+ $EN_DIS
+**/
+ UINT8 PcdEnableEmmc;
+
+/** Offset 0x002E - LAN Controllers
+ Enable / Disable LAN controllers, refer to FSP Integration Guide for details.
+ 0:Disable LAN 0 & LAN 1, 1:Enable LAN 0 & LAN 1, 2:Disable LAN 1 only
+**/
+ UINT8 PcdEnableGbE;
+
+/** Offset 0x002F
+**/
+ UINT32 PcdFiaMuxConfigRequestPtr;
+
+/** Offset 0x0033
+**/
+ UINT8 UnusedUpdSpace0[4];
+
+/** Offset 0x0037 - PCIe Root Port 0 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
+**/
+ UINT8 PcdPcieRootPort0DeEmphasis;
+
+/** Offset 0x0038 - PCIe Root Port 1 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
+**/
+ UINT8 PcdPcieRootPort1DeEmphasis;
+
+/** Offset 0x0039 - PCIe Root Port 2 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
+**/
+ UINT8 PcdPcieRootPort2DeEmphasis;
+
+/** Offset 0x003A - PCIe Root Port 3 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
+**/
+ UINT8 PcdPcieRootPort3DeEmphasis;
+
+/** Offset 0x003B - PCIe Root Port 4 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
+**/
+ UINT8 PcdPcieRootPort4DeEmphasis;
+
+/** Offset 0x003C - PCIe Root Port 5 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
+**/
+ UINT8 PcdPcieRootPort5DeEmphasis;
+
+/** Offset 0x003D - PCIe Root Port 6 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
+**/
+ UINT8 PcdPcieRootPort6DeEmphasis;
+
+/** Offset 0x003E - PCIe Root Port 7 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
+**/
+ UINT8 PcdPcieRootPort7DeEmphasis;
+
+/** Offset 0x003F
+**/
+ UINT8 UnusedUpdSpace1;
+
+/** Offset 0x0040
+**/
+ UINT32 PcdEMMCDLLConfigPtr;
+
+/** Offset 0x0044 - Disable Monitor MWAIT
+ Enable / Disable the Monitor-MWAIT Instruction
+ $EN_DIS
+**/
+ UINT8 PcdDisableMonitorFSM;
+
+/** Offset 0x0045
+**/
+ UINT8 UnusedUpdSpace2[155];
+
+/** Offset 0x00E0
+**/
+ UINT8 ReservedSiliconInitUpd[16];
+} FSPS_CONFIG;
+
+/** Fsp S UPD Configuration
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+ FSP_UPD_HEADER FspUpdHeader;
+
+/** Offset 0x0020
+**/
+ FSPS_CONFIG FspsConfig;
+
+/** Offset 0x00F0
+**/
+ UINT8 UnusedUpdSpace3[14];
+
+/** Offset 0x00FE
+**/
+ UINT16 UpdTerminator;
+} FSPS_UPD;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FsptUpd.h
new file mode 100644
index 0000000..23b4a04
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FsptUpd.h
@@ -0,0 +1,108 @@
+/** @file
+
+Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPTUPD_H__
+#define __FSPTUPD_H__
+
+#include <FspUpd.h>
+
+#pragma pack(1)
+
+/** FSP-T Core UPD
+**/
+typedef struct {
+
+/** Offset 0x0020
+**/
+ UINT32 MicrocodeRegionBase;
+
+/** Offset 0x0024
+**/
+ UINT32 MicrocodeRegionLength;
+
+/** Offset 0x0028
+**/
+ UINT32 CodeRegionBase;
+
+/** Offset 0x002C
+**/
+ UINT32 CodeRegionLength;
+
+/** Offset 0x0030
+**/
+ UINT8 Reserved1[16];
+} FSPT_CORE_UPD;
+
+/** FSP-T Configuration
+**/
+typedef struct {
+
+/** Offset 0x0040 - Disable Port80 output in FSP-T
+ Select Port80 Control in FSP-T (0:VPD-Style, 1:Enable Port80 Output, 2:Disable Port80
+ Output, refer to FSP Integration Guide for details
+ 0:VPD-Style, 1:Enable Port80 Output[Default], 2:Disable Port80 Output
+**/
+ UINT8 PcdFsptPort80RouteDisable;
+
+/** Offset 0x0041
+**/
+ UINT8 ReservedTempRamInitUpd[31];
+} FSPT_CONFIG;
+
+/** Fsp T UPD Configuration
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+ FSP_UPD_HEADER FspUpdHeader;
+
+/** Offset 0x0020
+**/
+ FSPT_CORE_UPD FsptCoreUpd;
+
+/** Offset 0x0040
+**/
+ FSPT_CONFIG FsptConfig;
+
+/** Offset 0x0060
+**/
+ UINT8 UnusedUpdSpace0[30];
+
+/** Offset 0x007E
+**/
+ UINT16 UpdTerminator;
+} FSPT_UPD;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_iiouds.h b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_iiouds.h
new file mode 100644
index 0000000..084f24c
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_iiouds.h
@@ -0,0 +1,246 @@
+/**
+Copyright (c) 2019-2020, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+**/
+
+
+#ifndef _HOB_IIOUDS_H_
+#define _HOB_IIOUDS_H_
+
+#include <fsp/util.h>
+//#include "pci_devs.h"
+
+#define FSP_HOB_IIO_UNIVERSAL_DATA_GUID { \
+ 0xa1, 0x96, 0xf3, 0x7f, 0x7d, 0xee, 0x1e, 0x43, \
+ 0xba, 0x53, 0x8f, 0xCa, 0x12, 0x7c, 0x44, 0xc0 \
+}
+
+#define NUMBER_PORTS_PER_SOCKET 21
+#define MAX_SOCKET CONFIG_MAX_SOCKET
+#define MAX_IIO MAX_SOCKET
+#define MAX_IIO_STACK 6
+#define MAX_KTI_PORTS 3
+#define MAX_IMC 2
+#define MAX_CH 6
+#define MC_MAX_NODE (MAX_SOCKET * MAX_IMC)
+#define SAD_RULES 24
+#define TDP_MAX_LEVEL 5
+
+#pragma pack(1)
+
+//--------------------------------------------------------------------------------------//
+// Structure definitions for Universal Data Store (UDS)
+//--------------------------------------------------------------------------------------//
+typedef struct uint64_t_struct {
+ uint32_t lo;
+ uint32_t hi;
+} UINT64_STRUCT;
+
+typedef struct {
+ uint8_t Device;
+ uint8_t Function;
+} IIO_PORT_INFO;
+
+typedef struct {
+ // TRUE, if the link is valid (i.e reached normal operation)
+ uint8_t Valid;
+ uint8_t PeerSocId; // Socket ID
+ uint8_t PeerSocType; // Socket Type (0 - CPU; 1 - IIO)
+ uint8_t PeerPort; // Port of the peer socket
+} QPI_PEER_DATA;
+
+typedef struct {
+ uint8_t Valid;
+ uint8_t SocketFirstBus;
+ uint8_t SocketLastBus;
+ uint8_t segmentSocket;
+ uint8_t PcieSegment;
+ UINT64_STRUCT SegMmcfgBase;
+ uint8_t stackPresentBitmap;
+ uint8_t StackBus[MAX_IIO_STACK];
+ uint8_t M2PciePresentBitmap;
+ uint8_t TotM3Kti;
+ uint8_t TotCha;
+ uint32_t ChaList;
+ uint32_t SocId;
+ QPI_PEER_DATA PeerInfo[MAX_KTI_PORTS]; // QPI LEP info
+} QPI_CPU_DATA;
+
+typedef struct {
+ uint8_t Valid;
+ uint8_t SocId;
+ QPI_PEER_DATA PeerInfo[MAX_SOCKET]; // QPI LEP info
+} QPI_IIO_DATA;
+
+typedef struct {
+ IIO_PORT_INFO PortInfo[NUMBER_PORTS_PER_SOCKET];
+} IIO_DMI_PCIE_INFO;
+
+typedef struct _STACK_RES {
+ uint8_t Personality;
+ uint8_t BusBase;
+ uint8_t BusLimit;
+ uint16_t PciResourceIoBase;
+ uint16_t PciResourceIoLimit;
+ uint32_t IoApicBase;
+ uint32_t IoApicLimit;
+ uint32_t PciResourceMem32Base;
+ uint32_t PciResourceMem32Limit;
+ uint64_t PciResourceMem64Base;
+ uint64_t PciResourceMem64Limit;
+ uint32_t VtdBarAddress;
+} STACK_RES;
+
+typedef struct {
+ uint8_t Valid;
+ int8_t SocketID; // Socket ID of the IIO (0..3)
+ uint8_t BusBase;
+ uint8_t BusLimit;
+ uint16_t PciResourceIoBase;
+ uint16_t PciResourceIoLimit;
+ uint32_t IoApicBase;
+ uint32_t IoApicLimit;
+ uint32_t PciResourceMem32Base;
+ uint32_t PciResourceMem32Limit;
+ uint64_t PciResourceMem64Base;
+ uint64_t PciResourceMem64Limit;
+ STACK_RES StackRes[MAX_IIO_STACK];
+ uint32_t RcBaseAddress;
+ IIO_DMI_PCIE_INFO PcieInfo;
+ uint8_t DmaDeviceCount;
+} IIO_RESOURCE_INSTANCE;
+
+typedef struct {
+ uint16_t PlatGlobalIoBase; // Global IO Base
+ uint16_t PlatGlobalIoLimit; // Global IO Limit
+ uint32_t PlatGlobalMmiolBase; // Global Mmiol base
+ uint32_t PlatGlobalMmiolLimit; // Global Mmiol limit
+ uint64_t PlatGlobalMmiohBase; // Global Mmioh Base [43:0]
+ uint64_t PlatGlobalMmiohLimit; // Global Mmioh Limit [43:0]
+ QPI_CPU_DATA CpuQpiInfo[MAX_SOCKET]; // QPI related info per CPU
+ QPI_IIO_DATA IioQpiInfo[MAX_SOCKET]; // QPI related info per IIO
+ uint32_t MemTsegSize;
+ uint32_t MemIedSize;
+ uint64_t PciExpressBase;
+ uint32_t PciExpressSize;
+ uint32_t MemTolm;
+ IIO_RESOURCE_INSTANCE IIO_resource[MAX_SOCKET];
+ uint8_t numofIIO;
+ uint8_t MaxBusNumber;
+ // This data array is valid only for SBSP, not for non-SBSP CPUs. <AS> for CpuSv
+ uint32_t packageBspApicID[MAX_SOCKET];
+ uint8_t EVMode;
+ uint8_t Pci64BitResourceAllocation;
+ uint8_t SkuPersonality[MAX_SOCKET];
+ uint8_t VMDStackEnable[MAX_IIO][MAX_IIO_STACK];
+ uint16_t IoGranularity;
+ uint32_t MmiolGranularity;
+ UINT64_STRUCT MmiohGranularity;
+ uint8_t RemoteRequestThreshold;
+ // bitmap of Softsku sockets with CPUs present detected
+ uint64_t softskuSocketPresentBitMap;
+ BOOLEAN Simics; // TRUE - Simics Environtment; FALSE - H\w
+} PLATFORM_DATA;
+
+typedef struct {
+ uint32_t FILLER_BUG;
+ // Current programmed CSI (or UPI) Link speed (Slow/Full speed mode)
+ uint8_t CurrentCsiLinkSpeed;
+ // Current requested CSI (or UPI) Link frequency (in GT)
+ uint8_t CurrentCsiLinkFrequency;
+ // output kti link enabled status for PM
+ uint32_t OutKtiPerLinkL1En[MAX_SOCKET];
+ uint8_t IsocEnable;
+ // Size of the memory range requested by ME FW, in MB
+ uint32_t meRequestedSize;
+ uint8_t DmiVc1;
+ uint8_t DmiVcm;
+ uint32_t CpuPCPSInfo;
+ uint8_t MinimumCpuStepping;
+ uint8_t LtsxEnable;
+ uint8_t MctpEn;
+ uint8_t cpuType;
+ uint8_t cpuSubType;
+ uint8_t SystemRasType;
+ // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC
+ uint8_t numCpus;
+ // Fused Core Mask in the package
+ uint32_t FusedCores[MAX_SOCKET];
+ // Current activated core Mask in the package
+ uint32_t ActiveCores[MAX_SOCKET];
+ // Package Max Non-turbo Ratio (per socket).
+ uint8_t MaxCoreToBusRatio[MAX_SOCKET];
+ // Package Maximum Efficiency Ratio (per socket).
+ uint8_t MinCoreToBusRatio[MAX_SOCKET];
+ uint8_t CurrentCoreToBusRatio; // Current system Core to Bus Ratio
+ // ISS Capable (system level) Bit[7:0] and current Config TDP Level Bit[15:8]
+ uint32_t IntelSpeedSelectCapable;
+ uint32_t IssConfigTdpLevelInfo; // get B2P CONFIG_TDP_GET_LEVELS_INFO
+ // get B2P CONFIG_TDP_GET_TDP_INFO
+ uint32_t IssConfigTdpTdpInfo[TDP_MAX_LEVEL];
+ // get B2P CONFIG_TDP_GET_POWER_INFO
+ uint32_t IssConfigTdpPowerInfo[TDP_MAX_LEVEL];
+ // get B2P CONFIG_TDP_GET_CORE_COUNT
+ uint8_t IssConfigTdpCoreCount[TDP_MAX_LEVEL];
+ // bitmap of sockets with CPUs present detected by QPI RC
+ uint32_t socketPresentBitMap;
+ // bitmap of NID w/ fpga present detected by QPI RC
+ uint32_t FpgaPresentBitMap;
+ uint16_t tolmLimit;
+ uint32_t tohmLimit;
+ uint32_t mmCfgBase;
+ uint32_t RcVersion;
+ uint8_t DdrXoverMode; // DDR 2.2 Mode
+ // For RAS
+ uint8_t bootMode;
+ uint8_t OutClusterOnDieEn; // Whether RC enabled COD support
+ uint8_t OutSncEn;
+ uint8_t OutNumOfCluster;
+ uint8_t imcEnabled[MAX_SOCKET][MAX_IMC];
+ uint8_t numChPerMC;
+ uint8_t maxCh;
+ uint8_t maxIMC;
+ uint16_t LlcSizeReg;
+ uint8_t chEnabled[MAX_SOCKET][MAX_CH];
+ uint8_t mcId[MAX_SOCKET][MAX_CH];
+ uint8_t memNode[MC_MAX_NODE];
+ uint8_t IoDcMode;
+ uint8_t CpuAccSupport;
+ uint8_t SmbusErrorRecovery;
+ uint8_t AepDimmPresent;
+} SYSTEM_STATUS;
+
+typedef struct {
+ PLATFORM_DATA PlatformData;
+ SYSTEM_STATUS SystemStatus;
+ uint32_t OemValue;
+} IIO_UDS;
+#pragma pack()
+
+void soc_display_iio_universal_data_hob(void);
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_memmap.h
new file mode 100644
index 0000000..954e43c
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_memmap.h
@@ -0,0 +1,119 @@
+/**
+Copyright (c) 2019-2020, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+**/
+
+
+#ifndef _MEMORY_MAP_GUID_H_
+#define _MEMORY_MAP_GUID_H_
+
+#define FSP_SYSTEM_MEMORYMAP_HOB_GUID { \
+ 0x15, 0x00, 0x87, 0xf8, 0x94, 0x69, 0x98, 0x4b, 0x95, 0xa2, \
+ 0xbd, 0x56, 0xda, 0x91, 0xc0, 0x7f \
+ }
+
+#define MEMTYPE_1LM_MASK (1 << 0)
+#define MEMTYPE_2LM_MASK (1 << 1)
+#define MEMTYPE_VOLATILE_MASK (MEMTYPE_1LM_MASK | MEMTYPE_2LM_MASK)
+
+#define MAX_IMC_PER_SOCKET 2
+#define MAX_SRAT_MEM_ENTRIES_PER_IMC 8
+#define MAX_ACPI_MEMORY_AFFINITY_COUNT ( \
+ MAX_SOCKET * MAX_IMC_PER_SOCKET * MAX_SRAT_MEM_ENTRIES_PER_IMC \
+ )
+
+/* ACPI SRAT Memory Flags */
+#define SRAT_ACPI_MEMORY_ENABLED (1 << 0)
+#define SRAT_ACPI_MEMORY_HOT_REMOVE_SUPPORTED (1 << 1)
+#define SRAT_ACPI_MEMORY_NONVOLATILE (1 << 2)
+
+#define MEM_TYPE_RESERVED (1 << 8)
+#define MEM_ADDR_64MB_SHIFT_BITS 26
+
+//
+// System Memory Map HOB information
+//
+
+#pragma pack(1)
+
+struct SystemMemoryMapElement {
+ UINT8 NodeId; // Node ID of the HA Owning the memory
+ UINT8 SocketId; // Socket Id of socket that has his memory - ONLY IN NUMA
+ UINT8 ImcInterBitmap; // IMC interleave bitmap for this DRAM rule - ONLY IN NUMA
+ UINT32 BaseAddress; // Base Address of the element in 64MB chunks
+ UINT32 ElementSize; // Size of this memory element in 64MB chunks
+ // Type of this memory element; Bit0: 1LM Bit1: 2LM Bit2: PMEM
+ // Bit3: PMEM-cache Bit4: BLK Window Bit5: CSR/Mailbox/Ctrl region
+ UINT16 Type;
+};
+
+struct SystemMemoryMapHob {
+ UINT32 lowMemBase; // Mem base in 64MB units for below 4GB mem.
+ UINT32 lowMemSize; // Mem size in 64MB units for below 4GB mem.
+ UINT32 highMemBase; // Mem base in 64MB units for above 4GB mem.
+ UINT32 highMemSize; // Mem size in 64MB units for above 4GB mem.
+ UINT32 asilLoMemBase; // Mem base in 64MB units for below 4GB mem.
+ UINT32 asilHiMemBase; // Mem base in 64MB units for above 4GB mem.
+ UINT32 asilLoMemSize; // Mem size in 64MB units for below 4GB mem.
+ UINT32 asilHiMemSize; // Mem size in 64MB units for above 4GB mem.
+
+ UINT32 memSize; // Total physical memory size
+ UINT16 memFreq; // Mem Frequency
+ UINT8 memMode; // 0 - Independent, 1 - Lockstep
+ UINT8 volMemMode; // 0 - 1LM, 1 - 2LM
+ UINT8 DimmType;
+ UINT16 DramType;
+ UINT8 DdrVoltage;
+ // If at least one Aep Dimm Present (used by Nfit), then this should get set
+ UINT8 AepDimmPresent;
+ UINT8 SADNum;
+ UINT8 XMPProfilesSup;
+ UINT8 cpuType;
+ UINT8 cpuStepping;
+ UINT8 SystemRasType;
+ UINT8 RasModesEnabled; // RAS modes that are enabled
+ UINT8 ExRasModesEnabled; // Extended RAS modes that are enabled
+ //RAS modes that are supported by current memory population.
+ UINT8 RasModesSupported;
+ // 0 - SNC disabled for this configuration, 1 - SNC enabled for this configuration
+ UINT8 sncEnabled;
+ UINT8 NumOfCluster;
+ UINT8 NumChPerMC;
+ UINT8 numberEntries; // Number of Memory Map Elements
+ UINT8 maxIMC;
+ UINT8 maxCh;
+ struct SystemMemoryMapElement Element[MAX_SOCKET * SAD_RULES];
+ UINT8 reserved1[982];
+ UINT8 reserved2[4901*MAX_SOCKET];
+ UINT8 reserved3[707];
+};
+
+#pragma pack()
+
+void soc_display_memmap_hob(void);
+
+#endif
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