Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35174 )
Change subject: mb/google/poppy/variant/nocturne: fix EC_SYNC_IRQ definition ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/35174/2/src/mainboard/google/poppy/... File src/mainboard/google/poppy/Kconfig:
https://review.coreboot.org/c/coreboot/+/35174/2/src/mainboard/google/poppy/... PS2, Line 197: select SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG If this is required this should be done at the SoC level. There is nothing mainboard-specific about this.
Actually, I see that it is already set here: https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/common/pch/.... Does that not take effect for KBL?
https://review.coreboot.org/c/coreboot/+/35174/2/src/mainboard/google/poppy/... File src/mainboard/google/poppy/chromeos.c:
https://review.coreboot.org/c/coreboot/+/35174/2/src/mainboard/google/poppy/... PS2, Line 36: EC_SYNC_IRQ Do you intend to pass the IRQ#, GPIO# or GPE# here?
https://review.coreboot.org/c/coreboot/+/35174/2/src/mainboard/google/poppy/... File src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/35174/2/src/mainboard/google/poppy/... PS2, Line 38: GPP_D17_IRQ Changing this would break the OS level interrupt resource: https://review.coreboot.org/cgit/coreboot.git/tree/src/ec/google/chromeec/ac...