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3 comments:
File src/mainboard/intel/adlrvp/devicetree.cb:
Patch Set #59, Line 58: # Clock source is shared with LAN and hence marked as free running.
--- a/src/mainboard/intel/adlrvp/devicetree.cb […]
You means CPU PCIE not work as well? Can this fix the SD card port? Could PCIE_RP_CLK_REQ_DETECT effect the CLK? Do we need this for the port have REQ?
File src/mainboard/intel/adlrvp/devicetree.cb:
register "pch_pcie_rp[PCH_RP(8)]" = "{
.flags = PCIE_RP_CLK_SRC_UNUSED,
}"
register "pcie_clk_config_flag[6]" = "PCIE_CLK_FREE_RUNNING"
I know we've gone over this several times. […]
Not only free running, we still have LAN as 0x70. Extra flag can help reduce the complexity
Patch Set #62, Line 72: .flags = PCIE_RP_CLK_SRC_UNUSED,
Does Optane need any CLKSRC?
This is share with SSD. This is co-layout for SSD and Optane. Since SSD is 4 lane optane is 2 lane.
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