Bernardo Perez Priego has uploaded this change for review.

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mb/google/drallion: Enable 360 sensor detection

Implementing logic to detect SKU model and enable ISH accordignly.

Change-Id: I22fafb43dce6545851883be556a02d65a01fc386
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
---
M src/mainboard/google/drallion/variants/drallion/gpio.c
M src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h
M src/soc/intel/cannonlake/romstage/fsp_params.c
3 files changed, 20 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/35303/1
diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c
index ebe5ee2..fc2c4dc 100644
--- a/src/mainboard/google/drallion/variants/drallion/gpio.c
+++ b/src/mainboard/google/drallion/variants/drallion/gpio.c
@@ -15,6 +15,10 @@

#include <variant/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
+#include <gpio.h>
+
+/* Sensor detection pin */
+#define SENSOR_DET_360 GPP_H5

/* Pad configuration in ramstage */
static const struct pad_config gpio_table[] = {
@@ -277,3 +281,9 @@
*num = ARRAY_SIZE(cros_gpios);
return cros_gpios;
}
+
+int get_sensor_detect(void)
+{
+ gpio_input(SENSOR_DET_360);
+ return gpio_get(SENSOR_DET_360);
+}
diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h b/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h
index 20cfbb8..6b7b64a 100644
--- a/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h
+++ b/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h
@@ -32,10 +32,14 @@
#define GPIO_MEM_CONFIG_3 GPP_F15
#define GPIO_MEM_CONFIG_4 GPP_F16

+#define IS_ISH_DEVICE_ENABLED (get_sensor_detect() == 0)
+
const struct pad_config *variant_gpio_table(size_t *num);
const struct pad_config *variant_early_gpio_table(size_t *num);

struct cros_gpio;
const struct cros_gpio *variant_cros_gpios(size_t *num);

+int get_sensor_detect(void);
+
#endif
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 3ba997d..1b673d9 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -23,9 +23,14 @@
#include <soc/pci_devs.h>
#include <soc/romstage.h>
#include <vendorcode/google/chromeos/chromeos.h>
+#include <variant/gpio.h>

#include "../chip.h"

+#ifndef IS_ISH_DEVICE_ENABLED
+#define IS_ISH_DEVICE_ENABLED (1)
+#endif
+
static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
{
unsigned int i;
@@ -82,7 +87,7 @@
if (!dev)
m_cfg->PchIshEnable = 0;
else
- m_cfg->PchIshEnable = dev->enabled;
+ m_cfg->PchIshEnable = dev->enabled && IS_ISH_DEVICE_ENABLED;

/* If HDA is enabled, enable HDA elements */
dev = pcidev_path_on_root(PCH_DEVFN_HDA);

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I22fafb43dce6545851883be556a02d65a01fc386
Gerrit-Change-Number: 35303
Gerrit-PatchSet: 1
Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Gerrit-MessageType: newchange