Elyes HAOUAS has uploaded this change for review.

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nb/intel/i945: Correct udelay for Netburst

NetBurst have FSB information at MSR_EBC_FREQUENCY_ID.

Change-Id: I588383dbdfd3d630c605c7d4d6014a3f82354e68
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
---
M src/northbridge/intel/i945/udelay.c
1 file changed, 12 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/27296/1

diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c
index 8447453..b02f13b 100644
--- a/src/northbridge/intel/i945/udelay.c
+++ b/src/northbridge/intel/i945/udelay.c
@@ -18,6 +18,7 @@
 #include <cpu/x86/tsc.h>
 #include <cpu/x86/msr.h>
 #include <cpu/intel/speedstep.h>
+#include <arch/cpu.h>
 
 /**
  * Intel Core(tm) CPUs always run the TSC at the maximum possible CPU clock
@@ -30,9 +31,18 @@
 	msr_t msr;
 	u32 fsb = 0, divisor;
 	u32 d;			/* ticks per us */
+	u8 fsbcfg;
+	const u32 eax = cpuid_eax(1);
 
-	msr = rdmsr(MSR_FSB_FREQ);
-	switch (msr.lo & 0x07) {
+	if (((eax >> 8) & 0xf) == 0xf) {
+		msr = rdmsr(MSR_EBC_FREQUENCY_ID);
+		fsbcfg = (msr.lo >> 16) & 0x7;
+	} else {
+		msr = rdmsr(MSR_FSB_FREQ);
+		fsbcfg = msr.lo & 0x7;
+	}
+
+	switch (fsbcfg) {
 	case 5:
 		fsb = 400;
 		break;

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