Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46841 )
Change subject: mb/google/volteer/var/terrador: Enable SaGv support ......................................................................
mb/google/volteer/var/terrador: Enable SaGv support
Enable SaGv for terrador.
BUG=b:171763116 BRANCH=volteer TEST="emerge-volteer coreboot" compiles successfully.
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: Ie00166a619424a67f70f870e55822ae2cc6d023d Reviewed-on: https://review.coreboot.org/c/coreboot/+/46841 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Derek Huang derek.huang@intel.corp-partner.google.com Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Paul Fagerburg pfagerburg@chromium.org --- M src/mainboard/google/volteer/variants/terrador/overridetree.cb 1 file changed, 0 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Paul Fagerburg: Looks good to me, but someone else must approve Derek Huang: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index fbf724f..d2e2d0b 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -14,8 +14,6 @@ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A / Type-C Port 0 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A / Type-C Port 1
- register "SaGv" = "SaGv_Disabled" - # Disable SRCCLKREQ1# register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED"