HAOUAS Elyes (ehaouas@noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16899
-gerrit
commit 790a9895895e7bb76e4991e0128bbc3074192824 Author: Elyes HAOUAS ehaouas@noos.fr Date: Wed Oct 5 22:17:30 2016 +0200
southbridge/nvidia: Remove commented code
Change-Id: Ice4a5cae1a289852895012bb55035707b54cefb5 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- src/southbridge/nvidia/ck804/early_setup.c | 4 --- src/southbridge/nvidia/ck804/lpc.c | 6 ---- src/southbridge/nvidia/ck804/pci.c | 7 ----- src/southbridge/nvidia/ck804/sata.c | 35 --------------------- src/southbridge/nvidia/ck804/smbus.h | 43 -------------------------- src/southbridge/nvidia/mcp55/bootblock.c | 7 +---- src/southbridge/nvidia/mcp55/early_setup_car.c | 19 ------------ src/southbridge/nvidia/mcp55/lpc.c | 14 --------- src/southbridge/nvidia/mcp55/mcp55.c | 11 ------- 9 files changed, 1 insertion(+), 145 deletions(-)
diff --git a/src/southbridge/nvidia/ck804/early_setup.c b/src/southbridge/nvidia/ck804/early_setup.c index abcb913..1d4999c 100644 --- a/src/southbridge/nvidia/ck804/early_setup.c +++ b/src/southbridge/nvidia/ck804/early_setup.c @@ -300,10 +300,6 @@ static void ck804_early_setup(void) setup_ss_table(CK804B_ANACTRL_IO_BASE + 0xc0, CK804B_ANACTRL_IO_BASE + 0xc4, CK804B_ANACTRL_IO_BASE + 0xc8, cpu_ss_tbl, 64); #endif
-#if 0 - dump_io_resources(ANACTRL_IO_BASE); - dump_io_resources(SYSCTRL_IO_BASE); -#endif }
static int ck804_early_setup_x(void) diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index d15ef8e..2b0bdd5 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -136,12 +136,6 @@ static void lpc_init(device_t dev) printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n", (on * 12) + (on >> 1), (on & 1) * 5); } -#if 0 - /* Enable Port 92 fast reset (default is enabled). */ - byte = pci_read_config8(dev, 0xe8); - byte |= ~(1 << 3); - pci_write_config8(dev, 0xe8, byte); -#endif
/* Set up NMI on errors. */ byte = inb(0x70); /* RTC70 */ diff --git a/src/southbridge/nvidia/ck804/pci.c b/src/southbridge/nvidia/ck804/pci.c index 8ccf80c..5f21e09 100644 --- a/src/southbridge/nvidia/ck804/pci.c +++ b/src/southbridge/nvidia/ck804/pci.c @@ -33,13 +33,6 @@ static void pci_init(struct device *dev) dword |= (1 << 30); /* Clear possible errors */ pci_write_config32(dev, 0x04, dword);
-#if 0 - word = pci_read_config16(dev, 0x48); - word |= (1 << 0); /* MRL2MRM */ - word |= (1 << 2); /* MR2MRM */ - pci_write_config16(dev, 0x48, word); -#endif - #if 1 dword = pci_read_config32(dev, 0x4c); dword |= 0x00440000; /* TABORT_SER_ENABLE Park Last Enable. */ diff --git a/src/southbridge/nvidia/ck804/sata.c b/src/southbridge/nvidia/ck804/sata.c index b67cf28..c5dc56e 100644 --- a/src/southbridge/nvidia/ck804/sata.c +++ b/src/southbridge/nvidia/ck804/sata.c @@ -51,13 +51,6 @@ static void sata_com_reset(struct device *dev, unsigned reset) *(base + 8) = dword; *(base + 0x48) = dword;
-#if 0 - udelay(1000); - dword &= ~(0xf); - *(base + 8) = dword; - *(base + 0x48) = dword; -#endif - if (reset) return;
@@ -109,17 +102,6 @@ static void sata_init(struct device *dev) dword |= (1 << 1); printk(BIOS_DEBUG, "SATA P\n"); } -#if 0 - /* Write back */ - dword |= (1 << 12); - dword |= (1 << 14); -#endif - -#if 0 - /* ADMA */ - dword |= (1 << 16); - dword |= (1 << 17); -#endif
#if 1 /* DO NOT relay OK and PAGE_FRNDLY_DTXFR_CNT. */ @@ -128,23 +110,6 @@ static void sata_init(struct device *dev) #endif pci_write_config32(dev, 0x50, dword);
-#if 0 - /* SLUMBER_DURING_D3 */ - dword = pci_read_config32(dev, 0x7c); - dword &= ~(1 << 4); - pci_write_config32(dev, 0x7c, dword); - - dword = pci_read_config32(dev, 0xd0); - dword &= ~(0xff << 24); - dword |= (0x68 << 24); - pci_write_config32(dev, 0xd0, dword); - - dword = pci_read_config32(dev, 0xe0); - dword &= ~(0xff << 24); - dword |= (0x68 << 24); - pci_write_config32(dev, 0xe0, dword); -#endif - dword = pci_read_config32(dev, 0xf8); dword |= 2; pci_write_config32(dev, 0xf8, dword); diff --git a/src/southbridge/nvidia/ck804/smbus.h b/src/southbridge/nvidia/ck804/smbus.h index 6d0c510..40b8cb7 100644 --- a/src/southbridge/nvidia/ck804/smbus.h +++ b/src/southbridge/nvidia/ck804/smbus.h @@ -34,25 +34,6 @@ static inline void smbus_delay(void) outb(0x80, 0x80); }
-#if 0 -/* Not needed, upon write to PRTCL, the status will be auto-cleared. */ -static int smbus_wait_until_ready(unsigned smbus_io_base) -{ - unsigned long loops; - loops = SMBUS_TIMEOUT; - do { - unsigned char val; - smbus_delay(); - val = inb(smbus_io_base + SMBHSTSTAT); - val &= 0x1f; - if (val == 0) - return 0; - outb(val, smbus_io_base + SMBHSTSTAT); - } while (--loops); - return -2; -} -#endif - static int smbus_wait_until_done(unsigned smbus_io_base) { unsigned long loops; @@ -72,12 +53,6 @@ static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) { unsigned char global_status_register, byte;
-#if 0 - /* Not needed, upon write to PRTCL, the status will be auto-cleared. */ - if (smbus_wait_until_ready(smbus_io_base) < 0) - return -2; -#endif - /* Set the device I'm talking to. */ outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD); smbus_delay(); @@ -112,12 +87,6 @@ static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, { unsigned global_status_register;
-#if 0 - /* Not needed, upon write to PRTCL, the status will be auto-cleared. */ - if (smbus_wait_until_ready(smbus_io_base) < 0) - return -2; -#endif - outb(val, smbus_io_base + SMBHSTDAT0); smbus_delay();
@@ -151,12 +120,6 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, { unsigned char global_status_register, byte;
-#if 0 - /* Not needed, upon write to PRTCL, the status will be auto-cleared. */ - if (smbus_wait_until_ready(smbus_io_base) < 0) - return -2; -#endif - /* Set the device I'm talking to. */ outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD); smbus_delay(); @@ -191,12 +154,6 @@ static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, { unsigned global_status_register;
-#if 0 - /* Not needed, upon write to PRTCL, the status will be auto-cleared. */ - if (smbus_wait_until_ready(smbus_io_base) < 0) - return -2; -#endif - outb(val, smbus_io_base + SMBHSTDAT0); smbus_delay();
diff --git a/src/southbridge/nvidia/mcp55/bootblock.c b/src/southbridge/nvidia/mcp55/bootblock.c index b77463a..6d24f56 100644 --- a/src/southbridge/nvidia/mcp55/bootblock.c +++ b/src/southbridge/nvidia/mcp55/bootblock.c @@ -28,13 +28,8 @@ static void mcp55_enable_rom(void) pci_devfn_t addr;
/* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ -#if 0 - /* Default MCP55 LPC single */ - addr = pci_locate_device(PCI_ID(0x10de, 0x0367), 0); -#else -// addr = pci_locate_device(PCI_ID(0x10de, 0x0360), 0); + addr = PCI_DEV(0, (MCP55_DEVN_BASE + 1), 0); -#endif
/* Set the 15MB enable bits. */ byte = pci_read_config8(addr, 0x88); diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c index 76947ec..7f1d03b 100644 --- a/src/southbridge/nvidia/mcp55/early_setup_car.c +++ b/src/southbridge/nvidia/mcp55/early_setup_car.c @@ -253,7 +253,6 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, #if CONFIG_MCP55_USE_AZA RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE,
- // RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), ~(1 << 14), (1 << 14), #endif
#ifdef MCP55_MB_SETUP @@ -326,22 +325,6 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, PCI_DEV(busn[j], devn[j], 0), io_base[j]); }
-#if 0 - for (j = 0; j < mcp55_num; j++) { - // PCI-E (XSPLL) SS table 0x40, x044, 0x48 - // SATA (SPPLL) SS table 0xb0, 0xb4, 0xb8 - // CPU (PPLL) SS table 0xc0, 0xc4, 0xc8 - setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0x40, - io_base[j] + ANACTRL_IO_BASE + 0x44, - io_base[j] + ANACTRL_IO_BASE + 0x48, pcie_ss_tbl, 64); - setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xb0, - io_base[j] + ANACTRL_IO_BASE + 0xb4, - io_base[j] + ANACTRL_IO_BASE + 0xb8, sata_ss_tbl, 64); - setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xc0, - io_base[j] + ANACTRL_IO_BASE + 0xc4, - io_base[j] + ANACTRL_IO_BASE + 0xc8, cpu_ss_tbl, 64); - } -#endif }
#ifndef HT_CHAIN_NUM_MAX @@ -405,7 +388,5 @@ out:
mcp55_early_clear_port(mcp55_num, busn, devn, io_base);
- // set_ht_link_mcp55(HT_CHAIN_NUM_MAX); - return 0; } diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index 824abc5..afc6e64 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -91,11 +91,6 @@ static void lpc_init(device_t dev)
lpc_common_init(dev, 1);
-#if 0 - /* Posted memory write enable. */ - byte = pci_read_config8(dev, 0x46); - pci_write_config8(dev, 0x46, byte | (1 << 0)); -#endif /* power after power fail */
#if 1 @@ -122,13 +117,6 @@ static void lpc_init(device_t dev) (on * 12) + (on >> 1), (on & 1) * 5); }
-#if 0 - /* Enable Port 92 fast reset (default is enabled). */ - byte = pci_read_config8(dev, 0xe8); - byte |= ~(1 << 3); - pci_write_config8(dev, 0xe8, byte); -#endif - /* Enable error reporting. */ /* Set up sync flood detected. */ byte = pci_read_config8(dev, 0x47); @@ -258,7 +246,6 @@ static struct device_operations lpc_ops = { .enable_resources = mcp55_lpc_enable_resources, .init = lpc_init, .scan_bus = scan_lpc_bus, -// .enable = mcp55_enable, .ops_pci = &mcp55_pci_ops, }; static const unsigned short lpc_ids[] = { @@ -295,7 +282,6 @@ static struct device_operations lpc_slave_ops = { .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_slave_init, -// .enable = mcp55_enable, .ops_pci = &mcp55_pci_ops, };
diff --git a/src/southbridge/nvidia/mcp55/mcp55.c b/src/southbridge/nvidia/mcp55/mcp55.c index cfe5e17..7c43fea 100644 --- a/src/southbridge/nvidia/mcp55/mcp55.c +++ b/src/southbridge/nvidia/mcp55/mcp55.c @@ -68,9 +68,7 @@ void mcp55_enable(device_t dev) if (dev->device == 0x0000) { vendorid = pci_read_config32(dev, PCI_VENDOR_ID); deviceid = (vendorid >> 16) & 0xffff; -// vendorid &= 0xffff; } else { -// vendorid = dev->vendor; deviceid = dev->device; }
@@ -200,15 +198,6 @@ void mcp55_enable(device_t dev) | (1 << 11) | (1 << 10) | (1 << 9)); pci_write_config32(sm_dev, 0xe8, final_reg); /* Enable all at first. */
-#if 0 - reg_old = reg = pci_read_config32(sm_dev, 0xe4); -// reg |= (1 << 0); - reg &= ~(0x3f << 4); - if (reg != reg_old) { - printk(BIOS_DEBUG, "mcp55.c pcie enabled\n"); - pci_write_config32(sm_dev, 0xe4, reg); - } -#endif }
if (!dev->enabled) {