Christian Walter has uploaded this change for review.
src/soc/intel/common/smbios: Add addtional infos to dimm_info
Added ECC Support and VDD Voltage to dimm_info struct. Now Bus Width
and ECCSupport will be propagated correctly in SMBIOS Type 17 Entry.
Change-Id: Ic6f0d4b223f1490ec7aa71a6105603635b514021
Signed-off-by: Christian Walter <christian.walter@9elements.com>
---
M src/arch/x86/smbios.c
M src/include/memory_info.h
M src/soc/intel/apollolake/meminit_util_apl.c
M src/soc/intel/apollolake/meminit_util_glk.c
M src/soc/intel/cannonlake/romstage/romstage.c
M src/soc/intel/common/smbios.c
M src/soc/intel/common/smbios.h
M src/soc/intel/icelake/romstage/romstage.c
M src/soc/intel/skylake/romstage/romstage_fsp20.c
9 files changed, 42 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/33031/1
diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c
index bf627f2..54c2b09 100644
--- a/src/arch/x86/smbios.c
+++ b/src/arch/x86/smbios.c
@@ -372,6 +372,11 @@
dimm->module_part_number[DIMM_INFO_PART_NUMBER_SIZE - 1] = '\0';
smbios_fill_dimm_part_number((char *)dimm->module_part_number, t);
+ /* Voltage Levels */
+ t->configured_voltage = dimm->vdd_voltage;
+ t->minimum_voltage = dimm->vdd_voltage;
+ t->maximum_voltage = dimm->vdd_voltage;
+
/* Synchronous = 1 */
t->type_detail = 0x0080;
/* no handle for error information */
diff --git a/src/include/memory_info.h b/src/include/memory_info.h
index 93c7b6b..c11e745 100644
--- a/src/include/memory_info.h
+++ b/src/include/memory_info.h
@@ -86,6 +86,10 @@
* See the smbios.h smbios_memory_bus_width enum.
*/
uint8_t bus_width;
+ /*
+ * Voltage Level
+ */
+ uint32_t vdd_voltage;
} __packed;
struct memory_info {
diff --git a/src/soc/intel/apollolake/meminit_util_apl.c b/src/soc/intel/apollolake/meminit_util_apl.c
index b272a99..cda7be5 100644
--- a/src/soc/intel/apollolake/meminit_util_apl.c
+++ b/src/soc/intel/apollolake/meminit_util_apl.c
@@ -80,6 +80,8 @@
if (!src_dimm->SizeInMb)
continue;
+ u8 memProfNum = memory_info_hob->MemoryProfile;
+
/* Populate the DIMM information */
dimm_info_fill(dest_dimm,
src_dimm->SizeInMb,
@@ -91,7 +93,9 @@
dram_part_num,
strlen(dram_part_num),
NULL, /* SPD not available */
- memory_info_hob->DataWidth);
+ memory_info_hob->DataWidth,
+ memory_info_hob->VddVoltage[memProfNum],
+ memory_info_hob->EccSupport);
index++;
}
}
diff --git a/src/soc/intel/apollolake/meminit_util_glk.c b/src/soc/intel/apollolake/meminit_util_glk.c
index 29dcd56..6940da6 100644
--- a/src/soc/intel/apollolake/meminit_util_glk.c
+++ b/src/soc/intel/apollolake/meminit_util_glk.c
@@ -86,6 +86,8 @@
if (!src_dimm->DimmCapacity)
continue;
+ u8 memProfNum = memory_info_hob->MemoryProfile;
+
/* Populate the DIMM information */
dimm_info_fill(dest_dimm,
src_dimm->DimmCapacity,
@@ -97,7 +99,9 @@
dram_part_num,
strlen(dram_part_num),
src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL,
- memory_info_hob->DataWidth);
+ memory_info_hob->DataWidth,
+ memory_info_hob->VddVoltage[memProfNum],
+ memory_info_hob->EccSupport);
index++;
}
}
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index 98d4c00..fa530a2 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -101,6 +101,8 @@
mainboard_get_dram_part_num(&dram_part_num,
&dram_part_num_len);
+ u8 memProfNum = memory_info_hob->MemoryProfile;
+
/* Populate the DIMM information */
dimm_info_fill(dest_dimm,
src_dimm->DimmCapacity,
@@ -112,7 +114,9 @@
dram_part_num,
dram_part_num_len,
src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL,
- memory_info_hob->DataWidth);
+ memory_info_hob->DataWidth,
+ memory_info_hob->VddVoltage[memProfNum],
+ memory_info_hob->EccSupport);
index++;
}
}
diff --git a/src/soc/intel/common/smbios.c b/src/soc/intel/common/smbios.c
index d89e9d5..f96e7f3 100644
--- a/src/soc/intel/common/smbios.c
+++ b/src/soc/intel/common/smbios.c
@@ -22,7 +22,8 @@
void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type,
u32 frequency, u8 rank_per_dimm, u8 channel_id, u8 dimm_id,
const char *module_part_num, size_t module_part_number_size,
- const u8 *module_serial_num, u16 data_width)
+ const u8 *module_serial_num, u16 data_width, u32 vdd_voltage,
+ bool ecc_support)
{
dimm->dimm_size = dimm_capacity;
dimm->ddr_type = ddr_type;
@@ -30,6 +31,8 @@
dimm->rank_per_dimm = rank_per_dimm;
dimm->channel_num = channel_id;
dimm->dimm_num = dimm_id;
+ dimm->vdd_voltage = vdd_voltage;
+
strncpy((char *)dimm->module_part_number,
module_part_num,
min(sizeof(dimm->module_part_number),
@@ -57,4 +60,7 @@
printk(BIOS_NOTICE, "Incorrect DIMM Data width: %u\n",
(unsigned int)data_width);
}
+
+ if (ecc_support)
+ dimm->bus_width |= 0x8;
}
diff --git a/src/soc/intel/common/smbios.h b/src/soc/intel/common/smbios.h
index 5824f5d..12b8da0 100644
--- a/src/soc/intel/common/smbios.h
+++ b/src/soc/intel/common/smbios.h
@@ -26,6 +26,7 @@
void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type,
u32 frequency, u8 rank_per_dimm, u8 channel_id, u8 dimm_id,
const char *module_part_num, size_t module_part_number_size,
- const u8 *module_serial_num, u16 data_width);
+ const u8 *module_serial_num, u16 data_width, u32 vdd_voltage,
+ bool ecc_support);
#endif /* _COMMON_SMBIOS_H_ */
diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c
index 179d99c..a09641c 100644
--- a/src/soc/intel/icelake/romstage/romstage.c
+++ b/src/soc/intel/icelake/romstage/romstage.c
@@ -86,6 +86,8 @@
if (src_dimm->Status != DIMM_PRESENT)
continue;
+ u8 memProfNum = memory_info_hob->MemoryProfile;
+
/* Populate the DIMM information */
dimm_info_fill(dest_dimm,
src_dimm->DimmCapacity,
@@ -97,7 +99,9 @@
(const char *)src_dimm->ModulePartNum,
sizeof(src_dimm->ModulePartNum),
src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL,
- memory_info_hob->DataWidth);
+ memory_info_hob->DataWidth,
+ memory_info_hob->VddVoltage[memProfNum],
+ memory_info_hob->EccSupport);
index++;
}
}
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index 96937d6..12ad757 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -115,6 +115,7 @@
ddr_type = MEMORY_TYPE_UNKNOWN;
break;
}
+ u8 memProfNum = memory_info_hob->MemoryProfile;
/* Populate the DIMM information */
dimm_info_fill(dest_dimm,
@@ -127,7 +128,9 @@
(const char *)src_dimm->ModulePartNum,
sizeof(src_dimm->ModulePartNum),
src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL,
- memory_info_hob->DataWidth);
+ memory_info_hob->DataWidth,
+ memory_info_hob->VddVoltage[memProfNum],
+ memory_info_hob->EccSupport);
index++;
}
}
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