1 comment:
File src/soc/intel/alderlake/romstage/fsp_params.c:
Patch Set #9, Line 40: config->PcieRp[i].clkreq
What is the FSP UPD expectation? I thought we had to add or subtract one somewhere since the number […]
I think you thought is PCIE port in schematic is 1-10 and CLKREQ/CLKSRC is 0-9. But we do subtract RP number in device tree is every project. Do you want keep the RP number same as schematic? Then we can subtract RP-1 here.
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