[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Correct SMBUS_SLAVE_ADDR definition

[Angel Pons (Code Review)]

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50941 )

Change subject: soc/intel/skylake: Correct SMBUS_SLAVE_ADDR definition
......................................................................

soc/intel/skylake: Correct SMBUS_SLAVE_ADDR definition

According to document 332691-003EN (SPT-H datasheet volume 2), the
hardware defaults to 0x44, which matches what newer platforms use.

Change-Id: I494587b0074ab3675c3e88676375f667e757cdf0
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50941
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: Michael Niewöhner 
Reviewed-by: Arthur Heymans 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/skylake/include/soc/smbus.h
1 file changed, 6 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Arthur Heymans: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved
  Michael Niewöhner: Looks good to me, approved

diff --git a/src/soc/intel/skylake/include/soc/smbus.h b/src/soc/intel/skylake/include/soc/smbus.h
index 00aae2c..bd86aca 100644
--- a/src/soc/intel/skylake/include/soc/smbus.h
+++ b/src/soc/intel/skylake/include/soc/smbus.h
@@ -17,7 +17,11 @@
 #define  TCO_INTRD_SEL_SMI		(1 << 2)
 #define  TCO_INTRD_SEL_INT		(1 << 1)

-/* SMBus I/O bits. */
-#define SMBUS_SLAVE_ADDR	0x24
+/*
+ * Default slave address value for PCH. This value is set to match default
+ * value set by hardware. It is useful since PCH is able to respond even
+ * before CPU is up. This is reset by RSMRST# but not by PLTRST#.
+ */
+#define SMBUS_SLAVE_ADDR		0x44

#endif