Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26859 )
Change subject: cpu/intel/haswell: Use C_ENVIRONMENT_BOOTBLOCK
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Patch Set 48:
(1 comment)
https://review.coreboot.org/#/c/26859/48/src/cpu/intel/car/non-evict/cache_a...
File src/cpu/intel/car/non-evict/cache_as_ram.S:
https://review.coreboot.org/#/c/26859/48/src/cpu/intel/car/non-evict/cache_a...
PS48, Line 36: #if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
why is it implemented in assembly? It could be part of soc early init.
The cache as ram code set's up those MTRR's after which they can't be used as an indication that the CPU has not been reset properly. Previously this was done in romcc code.
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