Attention is currently required from: Benjamin Doron, Felix Held, Fred Reitberger, Jason Glenesk, Jérémy Compostella, Matt DeVillier.

Benjamin Doron uploaded patch set #2 to this change.

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The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins)

[DNM] treewide: Prepare mode switch code for dynamically generated paging

Make the long mode entry code generic to prepare for dynamically
generated page tables. entry64.inc now expects the caller to load
the page tables' address into the EAX register.

The mode switch assembly now stashes the previous page table address to
restore after the protected mode call is incomplete. Follow-up changes
will program/use dynamically generated tables for long mode calls,
the SIPI vector and SMM stub.

While we're here, fix qemu-x86 code to only get page table address and
include entry64.inc for 64-bit environments.

This is not a functional change.

Untested.

Change-Id: I1ef7c8bee0c38395d5436f6479f11b3a4208f53e
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
---
M src/cpu/intel/car/core2/cache_as_ram.S
M src/cpu/intel/car/non-evict/cache_as_ram.S
M src/cpu/intel/car/p4-netburst/cache_as_ram.S
M src/cpu/qemu-x86/cache_as_ram_bootblock.S
M src/cpu/x86/64bit/entry64.inc
M src/cpu/x86/64bit/mode_switch.S
M src/cpu/x86/64bit/mode_switch2.S
M src/cpu/x86/64bit/pt.S
M src/cpu/x86/sipi_vector.S
M src/cpu/x86/smm/smm_stub.S
M src/soc/amd/common/block/cpu/noncar/pre_c.S
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
12 files changed, 39 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/79226/2

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