Matt DeVillier has uploaded this change for review.
sb/intel/bd82x6x: fix linking for non-native raminit case
Commit 45d4b17 [nb/intel/sandybridge: Move southbridge code to bd82x6x]
moved early_pch_init() to the southbridge, but failed to include
early_pch.c for the non-native raminit case, which now fails to link.
As all boards default to native raminit, this was missed by the autobuilder.
Adjust early_pch.c to be compiled regardles of ram init type used
Test: build/boot google/stout with MRC ram init selected
Change-Id: I50db30fda9a1099fb434c04ea97bcc38f8455233
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
---
M src/southbridge/intel/bd82x6x/Makefile.inc
1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/32382/1
diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc
index 7ce3da7..a950e5c 100644
--- a/src/southbridge/intel/bd82x6x/Makefile.inc
+++ b/src/southbridge/intel/bd82x6x/Makefile.inc
@@ -40,9 +40,10 @@
romstage-y += early_smbus.c me_status.c
romstage-y += early_spi.c
romstage-y += early_rcba.c
+romstage-y += early_pch.c
ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y)
-romstage-y += early_thermal.c early_pch.c early_me.c early_usb.c
+romstage-y += early_thermal.c early_me.c early_usb.c
else
romstage-y += early_me_mrc.c early_usb_mrc.c
endif
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