5 comments:
File src/mainboard/google/drallion/romstage.c:
Patch Set #1, Line 65: memupd->FspmConfig.DisableDimmChannel0 = gpio_get(GPP_F1)? 0 : 3;
spaces required around that '?' (ctx:VxW)
Ack
Patch Set #1, Line 66: memupd->FspmConfig.DisableDimmChannel1 = gpio_get(GPP_F2)? 0 : 3;
spaces required around that '?' (ctx:VxW)
Ack
File src/mainboard/google/drallion/romstage.c:
spd[0] = {
.read_type = READ_SMBUS,
.spd_spec = {.spd_smbus_address = 0xa0},
},
.spd[1] = {.read_type = NOT_EXISTING},
.spd[2] = {
.read_type = READ_SMBUS,
.spd_spec = {.spd_smbus_address = 0xa4},
},
.spd[3] = {.read_type = NOT_EXISTING},
No, as I said, this currently copy from Sarien and we will remove this in Drallion, we only use on-b […]
Ack
Patch Set #2, Line 65: GPP_F1
Yes, I will keep this CL until I verified in factory. We are going to modify GPIO table. […]
Ack
Patch Set #2, Line 65: DisableDimmChannel0
I meant something like this: […]
Ack
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