Patrick Georgi submitted this change.

View Change

Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved Mimoja: Looks good to me, but someone else must approve Frans Hendriks: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved
nb/{haswell,i945,sandybridge}: Drop outdated comment

'e7525/northbridge.c' does not exist anymore.

Change-Id: I5520760f59a3c6f89afb1360b12bd9763fba562a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37653
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Mimoja <coreboot@mimoja.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
M src/northbridge/intel/haswell/northbridge.c
M src/northbridge/intel/i945/northbridge.c
M src/northbridge/intel/sandybridge/northbridge.c
3 files changed, 0 insertions(+), 3 deletions(-)

diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index c047c39..1efa660 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -92,7 +92,6 @@

/* TODO We could determine how many PCIe busses we need in
* the bar. For now that number is hardcoded to a max of 64.
- * See e7525/northbridge.c for an example.
*/
static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index dde1b11..bcecd88 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -165,7 +165,6 @@

/* TODO We could determine how many PCIe busses we need in
* the bar. For now that number is hardcoded to a max of 64.
- * See e7525/northbridge.c for an example.
*/
static struct device_operations pci_domain_ops = {
.read_resources = mch_domain_read_resources,
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 6337d69..b34f07d 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -258,7 +258,6 @@

/* TODO We could determine how many PCIe busses we need in
* the bar. For now that number is hardcoded to a max of 64.
- * See e7525/northbridge.c for an example.
*/
static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,

To view, visit change 37653. To unsubscribe, or for help writing mail filters, visit settings.

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I5520760f59a3c6f89afb1360b12bd9763fba562a
Gerrit-Change-Number: 37653
Gerrit-PatchSet: 3
Gerrit-Owner: HAOUAS Elyes <ehaouas@noos.fr>
Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com>
Gerrit-Reviewer: Frans Hendriks <fhendriks@eltan.com>
Gerrit-Reviewer: HAOUAS Elyes <ehaouas@noos.fr>
Gerrit-Reviewer: Mimoja <coreboot@mimoja.de>
Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com>
Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net>
Gerrit-MessageType: merged