CK HU has uploaded this change for review.

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soc/mediatek/mt8192: Add a stub implementation of the MT8192 SoC

Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: I2cf68805532f70f072b4e9a21ee61e2ebe4ebd9d
---
A src/soc/mediatek/mt8192/Makefile.inc
1 file changed, 31 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/43962/1

diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc
new file mode 100644
index 0000000..25574c9
--- /dev/null
+++ b/src/soc/mediatek/mt8192/Makefile.inc
@@ -0,0 +1,31 @@
+ifeq ($(CONFIG_SOC_MEDIATEK_MT8192),y)
+
+bootblock-y += ../common/gpio.c gpio.c
+bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
+bootblock-y += ../common/timer.c
+bootblock-y += ../common/uart.c
+
+verstage-y += ../common/gpio.c gpio.c
+verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
+verstage-y += ../common/timer.c
+verstage-y += ../common/uart.c
+
+romstage-y += ../common/cbmem.c
+romstage-y += emi.c
+romstage-y += ../common/gpio.c gpio.c
+romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
+romstage-y += ../common/timer.c
+romstage-y += ../common/uart.c
+
+ramstage-y += ../common/gpio.c gpio.c
+ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
+ramstage-y += ../common/timer.c
+ramstage-y += ../common/uart.c
+
+CPPFLAGS_common += -Isrc/soc/mediatek/mt8192/include
+CPPFLAGS_common += -Isrc/soc/mediatek/common/include
+
+$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
+	./util/mtkheader/gen-bl-img.py mt8183 sf $< $@
+
+endif

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