Daniel Maslowski has uploaded this change for review.

View Change

mainboards: add GIGABYTE P34G v2

Change-Id: I5d83fbc4e402a9c0819947b8ea1ef2e480c3e5cb
Signed-off-by: Daniel Maslowski <info@orangecms.org>
---
M 3rdparty/blobs
A src/mainboard/gigabyte/p34g-v2/Kconfig
A src/mainboard/gigabyte/p34g-v2/Kconfig.name
A src/mainboard/gigabyte/p34g-v2/Makefile.inc
A src/mainboard/gigabyte/p34g-v2/acpi/ec.asl
A src/mainboard/gigabyte/p34g-v2/acpi/platform.asl
A src/mainboard/gigabyte/p34g-v2/acpi/superio.asl
A src/mainboard/gigabyte/p34g-v2/acpi/thermal.asl
A src/mainboard/gigabyte/p34g-v2/acpi_tables.c
A src/mainboard/gigabyte/p34g-v2/board_info.txt
A src/mainboard/gigabyte/p34g-v2/cmos.default
A src/mainboard/gigabyte/p34g-v2/cmos.layout
A src/mainboard/gigabyte/p34g-v2/devicetree.cb
A src/mainboard/gigabyte/p34g-v2/dsdt.asl
A src/mainboard/gigabyte/p34g-v2/gma-mainboard.ads
A src/mainboard/gigabyte/p34g-v2/gpio.c
A src/mainboard/gigabyte/p34g-v2/hda_verb.c
A src/mainboard/gigabyte/p34g-v2/mainboard.c
A src/mainboard/gigabyte/p34g-v2/romstage.c
A src/mainboard/gigabyte/p34g-v2/thermal.h
M src/southbridge/intel/lynxpoint/lpc.c
21 files changed, 1,093 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/36072/1
diff --git a/3rdparty/blobs b/3rdparty/blobs
index 62aa0e0..5afdf04 160000
--- a/3rdparty/blobs
+++ b/3rdparty/blobs
@@ -1 +1 @@
-Subproject commit 62aa0e0c54295bbb7b1a3e5e73f960bafdb59d04
+Subproject commit 5afdf04b4fce5cff33d704d1b474fd9609cbab15
diff --git a/src/mainboard/gigabyte/p34g-v2/Kconfig b/src/mainboard/gigabyte/p34g-v2/Kconfig
new file mode 100644
index 0000000..f625052
--- /dev/null
+++ b/src/mainboard/gigabyte/p34g-v2/Kconfig
@@ -0,0 +1,55 @@
+if BOARD_GIGABYTE_P34G_V2
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select CPU_INTEL_HASWELL
+ select NORTHBRIDGE_INTEL_HASWELL
+ select SOUTHBRIDGE_INTEL_LYNXPOINT
+ select INTEL_INT15
+ select INTEL_GMA_HAVE_VBT
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_TABLES
+ select HAVE_ACPI_RESUME
+ select EC_ACPI
+ select SUPERIO_ITE_IT8587E
+ select MAINBOARD_HAS_LIBGFXINIT
+ select SERIRQ_CONTINUOUS_MODE
+ select SYSTEM_TYPE_LAPTOP
+ select TSC_MONOTONIC_TIMER
+
+config MAINBOARD_DIR
+ string
+ default gigabyte/p34g-v2
+
+config GFX_GMA_CPU_VARIANT
+ string
+ default "Normal"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "P34G_V2"
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,0416.rom"
+
+config VGA_BIOS_ID
+ string
+ default "8086,0416"
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+ hex
+ default 0xa456
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ default 0x1458
+
+config MAX_CPUS
+ int
+ default 8
+
+config USBDEBUG_HCD_INDEX # FIXME: check this
+ int
+ default 2
+endif
diff --git a/src/mainboard/gigabyte/p34g-v2/Kconfig.name b/src/mainboard/gigabyte/p34g-v2/Kconfig.name
new file mode 100644
index 0000000..e6a7665
--- /dev/null
+++ b/src/mainboard/gigabyte/p34g-v2/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_GIGABYTE_P34G_V2
+ bool "P34G_V2"
diff --git a/src/mainboard/gigabyte/p34g-v2/Makefile.inc b/src/mainboard/gigabyte/p34g-v2/Makefile.inc
new file mode 100644
index 0000000..ebe01ae
--- /dev/null
+++ b/src/mainboard/gigabyte/p34g-v2/Makefile.inc
@@ -0,0 +1,2 @@
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/gigabyte/p34g-v2/acpi/ec.asl b/src/mainboard/gigabyte/p34g-v2/acpi/ec.asl
new file mode 100644
index 0000000..aa083da
--- /dev/null
+++ b/src/mainboard/gigabyte/p34g-v2/acpi/ec.asl
@@ -0,0 +1,22 @@
+Device(EC)
+{
+ Name (_HID, EISAID("PNP0C09"))
+ Name (_UID, 0)
+ Name (_GPE, 23)
+ Device (BAT0)
+ {
+ Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ /* vendor:
+ If ((BNUM & One))
+ {
+ Return (0x1F)
+ }
+ Return (0x0B)
+ */
+ Return (Zero)
+ }
+ }
+}
diff --git a/src/mainboard/gigabyte/p34g-v2/acpi/platform.asl b/src/mainboard/gigabyte/p34g-v2/acpi/platform.asl
new file mode 100644
index 0000000..c2862c9
--- /dev/null
+++ b/src/mainboard/gigabyte/p34g-v2/acpi/platform.asl
@@ -0,0 +1,10 @@
+Method(_WAK,1)
+{
+ /* FIXME: EC support */
+ Return(Package(){0,0})
+}
+
+Method(_PTS,1)
+{
+ /* FIXME: EC support */
+}
diff --git a/src/mainboard/gigabyte/p34g-v2/acpi/superio.asl b/src/mainboard/gigabyte/p34g-v2/acpi/superio.asl
new file mode 100644
index 0000000..f2b35ba
--- /dev/null
+++ b/src/mainboard/gigabyte/p34g-v2/acpi/superio.asl
@@ -0,0 +1 @@
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/gigabyte/p34g-v2/acpi/thermal.asl b/src/mainboard/gigabyte/p34g-v2/acpi/thermal.asl
new file mode 100644
index 0000000..93421d2
--- /dev/null
+++ b/src/mainboard/gigabyte/p34g-v2/acpi/thermal.asl
@@ -0,0 +1,109 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+// Thermal Zone
+
+External (\PPKG, MethodObj)
+
+#define HAVE_THERMALZONE
+Scope (\_TZ)
+{
+ ThermalZone (THRM)
+ {
+ Name (_TC1, 0x08)
+ Name (_TC2, 0x08)
+
+ // Ignore critical temps for the first few reads
+ // at boot to prevent unexpected shutdown
+ Name (IRDC, 4)
+ Name (CRDC, 0)
+
+ // Thermal zone polling frequency: 10 seconds
+ Name (_TZP, 100)
+
+ // Thermal sampling period for passive cooling: 2 seconds
+ Name (_TSP, 20)
+
+ // Convert from Degrees C to 1/10 Kelvin for ACPI
+ Method (CTOK, 1) {
+ // 10th of Degrees C
+ Multiply (Arg0, 10, Local0)
+
+ // Convert to Kelvin
+ Add (Local0, 2732, Local0)
+
+ Return (Local0)
+ }
+
+ // Threshold for OS to shutdown
+ Method (_CRT, 0, Serialized)
+ {
+ Return (CTOK (\TCRT))
+ }
+
+ // Threshold for passive cooling
+ Method (_PSV, 0, Serialized)
+ {
+ Return (CTOK (\TPSV))
+ }
+
+ // Processors used for passive cooling
+ Method (_PSL, 0, Serialized)
+ {
+ Return (\PPKG ())
+ }
+/*
+ Method (_AC0) {
+ If (LLessEqual (\FLVL, 0)) {
+ Return (CTOK (\F0OF))
+ } Else {
+ Return (CTOK (\F0ON))
+ }
+ }
+
+ Method (_AC1) {
+ If (LLessEqual (\FLVL, 1)) {
+ Return (CTOK (\F1OF))
+ } Else {
+ Return (CTOK (\F1ON))
+ }
+ }
+
+ Method (_AC2) {
+ If (LLessEqual (\FLVL, 2)) {
+ Return (CTOK (\F2OF))
+ } Else {
+ Return (CTOK (\F2ON))
+ }
+ }
+
+ Method (_AC3) {
+ If (LLessEqual (\FLVL, 3)) {
+ Return (CTOK (\F3OF))
+ } Else {
+ Return (CTOK (\F3ON))
+ }
+ }
+
+ Method (_AC4) {
+ If (LLessEqual (\FLVL, 4)) {
+ Return (CTOK (\F4OF))
+ } Else {
+ Return (CTOK (\F4ON))
+ }
+ }
+*/
+ }
+}
diff --git a/src/mainboard/gigabyte/p34g-v2/acpi_tables.c b/src/mainboard/gigabyte/p34g-v2/acpi_tables.c
new file mode 100644
index 0000000..f5e30b6
--- /dev/null
+++ b/src/mainboard/gigabyte/p34g-v2/acpi_tables.c
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/lynxpoint/nvs.h>
+
+#include "thermal.h"
+
+static global_nvs_t *gnvs_;
+
+static void acpi_update_thermal_table(global_nvs_t *gnvs)
+{
+ gnvs->f4of = FAN4_THRESHOLD_OFF;
+ gnvs->f4on = FAN4_THRESHOLD_ON;
+
+ gnvs->f3of = FAN3_THRESHOLD_OFF;
+ gnvs->f3on = FAN3_THRESHOLD_ON;
+
+ gnvs->f2of = FAN2_THRESHOLD_OFF;
+ gnvs->f2on = FAN2_THRESHOLD_ON;
+
+ gnvs->f1of = FAN1_THRESHOLD_OFF;
+ gnvs->f1on = FAN1_THRESHOLD_ON;
+
+ gnvs->f0of = FAN0_THRESHOLD_OFF;
+ gnvs->f0on = FAN0_THRESHOLD_ON;
+
+ gnvs->tcrt = CRITICAL_TEMPERATURE;
+ gnvs->tpsv = PASSIVE_TEMPERATURE;
+ gnvs->tmax = MAX_TEMPERATURE;
+ gnvs->flvl = 5; // Fan level
+}
+
+/* FIXME: check this function. */
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ gnvs_ = gnvs;
+
+ /* Disable USB ports in S3 by default */
+ gnvs->s3u0 = 0;
+ gnvs->s3u1 = 0;
+
+ /* Disable USB ports in S5 by default */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ // the lid is open by default.
+ gnvs->lids = 1;
+
+ gnvs->tcrt = CRITICAL_TEMPERATURE;
+ gnvs->tpsv = PASSIVE_TEMPERATURE;
+
+ acpi_update_thermal_table(gnvs);
+}
diff --git a/src/mainboard/gigabyte/p34g-v2/board_info.txt b/src/mainboard/gigabyte/p34g-v2/board_info.txt
new file mode 100644
index 0000000..9135e44
--- /dev/null
+++ b/src/mainboard/gigabyte/p34g-v2/board_info.txt
@@ -0,0 +1,8 @@
+Category: laptop
+Board URL: https://www.gigabyte.com/Laptop/P34G-v2
+Board name: Gigabyte P34G v2 GA-R3456R
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2013
diff --git a/src/mainboard/gigabyte/p34g-v2/cmos.default b/src/mainboard/gigabyte/p34g-v2/cmos.default
new file mode 100644
index 0000000..f404714
--- /dev/null
+++ b/src/mainboard/gigabyte/p34g-v2/cmos.default
@@ -0,0 +1,5 @@
+boot_option=Fallback
+debug_level=Debug
+nmi=Enable
+power_on_after_fail=Keep
+hide_ast2400=Disable
diff --git a/src/mainboard/gigabyte/p34g-v2/cmos.layout b/src/mainboard/gigabyte/p34g-v2/cmos.layout
new file mode 100644
index 0000000..cce1f18
--- /dev/null
+++ b/src/mainboard/gigabyte/p34g-v2/cmos.layout
@@ -0,0 +1,97 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+## Copyright (C) 2014 Vladimir Serbinenko
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+# Status Register A
+# -----------------------------------------------------------------
+# Status Register B
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 3 boot_option
+388 4 h 0 reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+#392 3 r 0 unused
+395 4 e 4 debug_level
+#399 1 r 0 unused
+
+#400 8 r 0 reserved for century byte
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 5 power_on_after_fail
+
+# coreboot config options: mainboard
+416 1 e 1 hide_ast2400
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+
+2 0 Enable
+2 1 Disable
+
+3 0 Fallback
+3 1 Normal
+
+4 0 Emergency
+4 1 Alert
+4 2 Critical
+4 3 Error
+4 4 Warning
+4 5 Notice
+4 6 Info
+4 7 Debug
+4 8 Spew
+
+5 0 Disable
+5 1 Enable
+5 2 Keep
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 423 984
diff --git a/src/mainboard/gigabyte/p34g-v2/devicetree.cb b/src/mainboard/gigabyte/p34g-v2/devicetree.cb
new file mode 100644
index 0000000..063ff5d
--- /dev/null
+++ b/src/mainboard/gigabyte/p34g-v2/devicetree.cb
@@ -0,0 +1,142 @@
+chip northbridge/intel/haswell # FIXME: check gfx.ndid and gfx.did
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
+ register "gfx.ndid" = "3"
+
+ register "gpu_cpu_backlight" = "0x00000200"
+ register "gpu_pch_backlight" = "0x04000000"
+
+ register "gpu_ddi_e_connected" = "1"
+ register "gpu_dp_b_hotplug" = "0x06"
+ register "gpu_dp_c_hotplug" = "0x00"
+ register "gpu_dp_d_hotplug" = "0x06"
+ register "gpu_panel_port_select" = "0"
+
+ # register value in hex: 6h for 500ms, i.e., (6-1)*100 - power_off_time
+ register "gpu_panel_power_cycle_delay" = "6" # T12
+ register "gpu_panel_power_up_delay" = "2000" # T3
+ register "gpu_panel_power_down_delay" = "5000" # T10
+ register "gpu_panel_power_backlight_on_delay" = "70" # T7
+ register "gpu_panel_power_backlight_off_delay" = "2100" # T9
+
+ device cpu_cluster 0x0 on
+ chip cpu/intel/haswell
+ device lapic 0x0 on end
+ device lapic 0xacac off end
+
+ register "c1_acpower" = "1"
+ register "c2_acpower" = "3"
+ register "c3_acpower" = "5"
+
+ register "c1_battery" = "1"
+ register "c2_battery" = "3"
+ register "c3_battery" = "5"
+ end
+ end
+
+ device domain 0x0 on
+ chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH
+ register "gen1_dec" = "0x00000061"
+ register "gen2_dec" = "0x00040069"
+ register "gen3_dec" = "0x00000000"
+ register "gen4_dec" = "0x00000000"
+ register "gpi7_routing" = "2"
+ register "pirqa_routing" = "0x0b"
+ register "pirqb_routing" = "0x03"
+ register "pirqc_routing" = "0x04"
+ register "pirqd_routing" = "0x0a"
+ register "pirqe_routing" = "0x80"
+ register "pirqf_routing" = "0x80"
+ register "pirqg_routing" = "0x05"
+ register "pirqh_routing" = "0x0b"
+ register "sata_ahci" = "1"
+ register "sata_port_map" = "0x3"
+ device pci 14.0 on # xHCI Controller
+ subsystemid 0x1458 0xa456
+ end
+ device pci 16.0 on # Management Engine Interface 1
+ subsystemid 0x1458 0xa456
+ end
+ device pci 16.1 off # Management Engine Interface 2
+ end
+ device pci 16.2 off # Management Engine IDE-R
+ end
+ device pci 16.3 off # Management Engine KT
+ end
+ # device pci 19.0 off # Intel Gigabit Ethernet # FIXME
+ # end
+ device pci 1a.0 on # USB2 EHCI #2
+ subsystemid 0x1458 0xa456
+ end
+ device pci 1b.0 on # High Definition Audio Audio controller
+ subsystemid 0x1458 0xa456
+ end
+ device pci 1c.0 on # PCIe Port #1
+ subsystemid 0x1458 0xa456
+ end
+ device pci 1c.1 on # PCIe Port #2
+ subsystemid 0x1458 0xa456
+ end
+ device pci 1c.2 on # PCIe Port #3
+ subsystemid 0x1458 0xa456
+ end
+ device pci 1c.3 off # PCIe Port #4
+ end
+ device pci 1c.4 off # PCIe Port #5
+ end
+ device pci 1c.5 off # PCIe Port #6
+ end
+ device pci 1c.6 off # PCIe Port #7
+ end
+ device pci 1c.7 off # PCIe Port #8
+ end
+ device pci 1d.0 on # USB2 EHCI #1
+ subsystemid 0x1458 0xa456
+ end
+ device pci 1f.0 on # LPC bridge PCI-LPC bridge
+ subsystemid 0x1458 0xa456
+ chip superio/ite/it8587e
+ # 0x4e according to superiotool.log
+ device pnp 4e.1 off end # UART 1
+ device pnp 4e.2 off end # UART 2
+ device pnp 4e.4 off end # sys wakeup
+ device pnp 4e.5 off end # mouse
+ device pnp 4e.6 on # keyboard FIXME: works?
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 4e.f off end # shared mem
+ device pnp 4e.10 off end # RTC
+ device pnp 4e.11 off end # PM1
+ device pnp 4e.12 off end # PM2
+ device pnp 4e.13 off end # SPI
+ device pnp 4e.17 off end # PM3
+ end
+ end
+ device pci 1f.2 on # SATA Controller 1
+ subsystemid 0x1458 0xa456
+ end
+ device pci 1f.3 on # SMBus
+ subsystemid 0x1458 0xa456
+ end
+ # device pci 1f.5 off # SATA Controller 2 # FIXME
+ # end
+ device pci 1f.6 on # Thermal
+ subsystemid 0x1458 0xa456
+ end
+ end
+ device pci 00.0 on # Host bridge Host bridge
+ subsystemid 0x1458 0xa456
+ end
+ device pci 01.0 on # PCIe Bridge for discrete graphics Unsupported PCI device 8086:0c01
+ subsystemid 0x1458 0xa456
+ end
+ device pci 02.0 on # Internal graphics VGA controller
+ subsystemid 0x1458 0xa456
+ end
+ device pci 03.0 on # Mini-HD audio Audio controller
+ subsystemid 0x8086 0x2010
+ end
+ end
+end
diff --git a/src/mainboard/gigabyte/p34g-v2/dsdt.asl b/src/mainboard/gigabyte/p34g-v2/dsdt.asl
new file mode 100644
index 0000000..47ee50c
--- /dev/null
+++ b/src/mainboard/gigabyte/p34g-v2/dsdt.asl
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
+
+#include <arch/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI 2.0 and up
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 // OEM revision
+)
+{
+ /* Some generic macros */
+ #include "acpi/platform.asl"
+
+ /* Super I/O, EC */
+ #include "acpi/superio.asl"
+ #include "acpi/ec.asl"
+
+ /* Thermal handler */
+ #include "acpi/thermal.asl"
+
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <southbridge/intel/lynxpoint/acpi/platform.asl>
+
+ /* global NVS and variables. */
+ #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
+ #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/haswell/acpi/haswell.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/lynxpoint/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/gigabyte/p34g-v2/gma-mainboard.ads b/src/mainboard/gigabyte/p34g-v2/gma-mainboard.ads
new file mode 100644
index 0000000..8a72a31
--- /dev/null
+++ b/src/mainboard/gigabyte/p34g-v2/gma-mainboard.ads
@@ -0,0 +1,30 @@
+--
+-- This file is part of the coreboot project.
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (DP1,
+ HDMI1,
+ Analog,
+ Internal,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/gigabyte/p34g-v2/gpio.c b/src/mainboard/gigabyte/p34g-v2/gpio.c
new file mode 100644
index 0000000..a700291
--- /dev/null
+++ b/src/mainboard/gigabyte/p34g-v2/gpio.c
@@ -0,0 +1,226 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_GPIO,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_NATIVE,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_NATIVE,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_NATIVE,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_NATIVE,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_OUTPUT,
+ .gpio11 = GPIO_DIR_INPUT,
+ .gpio12 = GPIO_DIR_OUTPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio8 = GPIO_LEVEL_LOW,
+ .gpio12 = GPIO_LEVEL_HIGH,
+ .gpio24 = GPIO_LEVEL_HIGH,
+ .gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio8 = GPIO_RESET_RSMRST,
+ .gpio24 = GPIO_RESET_RSMRST,
+ .gpio30 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio1 = GPIO_INVERT,
+ .gpio3 = GPIO_INVERT,
+ .gpio7 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_NATIVE,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_NATIVE,
+ .gpio46 = GPIO_MODE_GPIO,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_GPIO,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_GPIO,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_GPIO,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_OUTPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_OUTPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio46 = GPIO_DIR_OUTPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio50 = GPIO_DIR_OUTPUT,
+ .gpio51 = GPIO_DIR_OUTPUT,
+ .gpio52 = GPIO_DIR_OUTPUT,
+ .gpio53 = GPIO_DIR_OUTPUT,
+ .gpio54 = GPIO_DIR_OUTPUT,
+ .gpio55 = GPIO_DIR_OUTPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio34 = GPIO_LEVEL_LOW,
+ .gpio35 = GPIO_LEVEL_HIGH,
+ .gpio37 = GPIO_LEVEL_LOW,
+ .gpio46 = GPIO_LEVEL_LOW,
+ .gpio50 = GPIO_LEVEL_LOW,
+ .gpio51 = GPIO_LEVEL_HIGH,
+ .gpio52 = GPIO_LEVEL_HIGH,
+ .gpio53 = GPIO_LEVEL_HIGH,
+ .gpio54 = GPIO_LEVEL_HIGH,
+ .gpio55 = GPIO_LEVEL_LOW,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+ .gpio46 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_GPIO,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_GPIO,
+ .gpio67 = GPIO_MODE_GPIO,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_NATIVE,
+ .gpio71 = GPIO_MODE_NATIVE,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_NATIVE,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio64 = GPIO_DIR_OUTPUT,
+ .gpio66 = GPIO_DIR_OUTPUT,
+ .gpio67 = GPIO_DIR_INPUT,
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+ .gpio64 = GPIO_LEVEL_LOW,
+ .gpio66 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/gigabyte/p34g-v2/hda_verb.c b/src/mainboard/gigabyte/p34g-v2/hda_verb.c
new file mode 100644
index 0000000..c2cb5a0
--- /dev/null
+++ b/src/mainboard/gigabyte/p34g-v2/hda_verb.c
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x80862807, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+
+ 0x00000004, /* Number of 4 dword sets */
+ /* NID 0x01: Subsystem ID. */
+ AZALIA_SUBVENDOR(0x0, 0x80860101),
+
+ /* NID 0x05. */
+ AZALIA_PIN_CFG(0x0, 0x05, 0x18560010),
+
+ /* NID 0x06. */
+ AZALIA_PIN_CFG(0x0, 0x06, 0x18560010),
+
+ /* NID 0x07. */
+ AZALIA_PIN_CFG(0x0, 0x07, 0x18560010),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/gigabyte/p34g-v2/mainboard.c b/src/mainboard/gigabyte/p34g-v2/mainboard.c
new file mode 100644
index 0000000..be4a5aa
--- /dev/null
+++ b/src/mainboard/gigabyte/p34g-v2/mainboard.c
@@ -0,0 +1,50 @@
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <ec/acpi/ec.h>
+#include <console/console.h>
+#include <pc80/keyboard.h>
+
+static void mainboard_init(struct device *dev)
+{
+ /* FIXME: trim this down or remove if necessary */
+ {
+ int i;
+ const u8 dmp[256] = {
+ /* 00 */ 0x0a, 0xe3, 0x5b, 0xa0, 0x80, 0x40, 0x60, 0x00, 0x00, 0x01, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
+ /* 10 */ 0x54, 0x10, 0xa7, 0x0c, 0xdb, 0x0b, 0x2c, 0x42, 0xa2, 0x01, 0x65, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 20 */ 0x60, 0x3b, 0x00, 0x00, 0x9a, 0x0b, 0x01, 0x01, 0x00, 0x00, 0x55, 0x34, 0x4e, 0x00, 0x00, 0x00,
+ /* 30 */ 0x47, 0x42, 0x54, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 40 */ 0x00, 0x00, 0x00, 0x00, 0x55, 0x34, 0x4e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 50 */ 0x00, 0x00, 0x00, 0x00, 0xa7, 0x0c, 0x54, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 60 */ 0x3a, 0x37, 0x3a, 0x03, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x0b, 0xdb,
+ /* 70 */ 0x00, 0x65, 0x00, 0x00, 0x0c, 0xa7, 0x00, 0x00, 0x0b, 0x9a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14,
+ /* 80 */ 0x01, 0x44, 0x02, 0x87, 0x03, 0xcb, 0x05, 0x0f, 0x06, 0x53, 0x0c, 0x05, 0x00, 0x00, 0x00, 0x00,
+ /* 90 */ 0x98, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ /* a0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* b0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* c0 */ 0x00, 0x44, 0x00, 0x08, 0x00, 0x10, 0x00, 0x20, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* d0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* e0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* f0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ };
+
+ printk(BIOS_DEBUG, "Replaying EC dump ...");
+ for (i = 0; i < 256; i++)
+ ec_write (i, dmp[i]);
+ printk(BIOS_DEBUG, "done\n");
+ }
+ pc_keyboard_init(NO_AUX_DEVICE);
+}
+
+static void mainboard_enable(struct device *dev)
+{
+ dev->ops->init = mainboard_init;
+
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/gigabyte/p34g-v2/romstage.c b/src/mainboard/gigabyte/p34g-v2/romstage.c
new file mode 100644
index 0000000..7e09a49
--- /dev/null
+++ b/src/mainboard/gigabyte/p34g-v2/romstage.c
@@ -0,0 +1,114 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <arch/romstage.h>
+#include <cpu/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/raminit.h>
+#include <southbridge/intel/common/gpio.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+
+// root complex base addresses
+static const struct rcba_config_instruction rcba_config[] = {
+ /* Device interrupt route registers */
+ RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)),
+ RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC)),
+ RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),
+ RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD)),
+ RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD)),
+ RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)),
+ RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQB)),
+ RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),
+
+ /* Disable unused devices (board specific, copied from Beltino) */
+ RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS),
+
+ RCBA_END_CONFIG,
+};
+
+void mainboard_config_superio(void)
+{
+}
+
+void mainboard_romstage_entry()
+{
+ struct pei_data pei_data = {
+ .pei_version = PEI_VERSION,
+ .mchbar = (uintptr_t)DEFAULT_MCHBAR,
+ .dmibar = (uintptr_t)DEFAULT_DMIBAR,
+ .epbar = DEFAULT_EPBAR,
+ .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
+ .smbusbar = SMBUS_IO_BASE,
+ .wdbbar = 0x4000000,
+ .wdbsize = 0x1000,
+ .hpet_address = HPET_ADDR,
+ .rcba = (uintptr_t)DEFAULT_RCBA,
+ .pmbase = DEFAULT_PMBASE,
+ .gpiobase = DEFAULT_GPIOBASE,
+ .temp_mmio_base = 0xfed08000,
+ .system_type = 1, /* desktop/server */
+ .tseg_size = CONFIG_SMM_TSEG_SIZE,
+ // left-shifted by 1 for mrc.bin
+ .spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 },
+ .ec_present = 0,
+ // 0 = leave channel enabled
+ // 1 = disable dimm 0 on channel
+ // 2 = disable dimm 1 on channel
+ // 3 = disable dimm 0+1 on channel
+ .dimm_channel0_disabled = 2,
+ .dimm_channel1_disabled = 2,
+ .max_ddr3_freq = 1600,
+ .usb2_ports = {
+ /* Length, Enable, OCn#, Location */
+ { 0x0040, 1, 0, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 0, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 1, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 2, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 3, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 3, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 4, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 4, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 5, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 5, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 6, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 6, USB_PORT_BACK_PANEL },
+ },
+ .usb3_ports = {
+ { 1, 0 },
+ { 1, 0 },
+ { 1, 1 },
+ { 1, 1 },
+ { 1, 2 },
+ { 1, 2 },
+ },
+ };
+
+ struct romstage_params romstage_params = {
+ .pei_data = &pei_data,
+ .gpio_map = &mainboard_gpio_map,
+ .rcba_config = &rcba_config[0],
+ };
+
+ /* SuperIO */
+ pch_enable_lpc();
+
+ /* Main romstage entry */
+ romstage_common(&romstage_params);
+}
diff --git a/src/mainboard/gigabyte/p34g-v2/thermal.h b/src/mainboard/gigabyte/p34g-v2/thermal.h
new file mode 100644
index 0000000..210c702
--- /dev/null
+++ b/src/mainboard/gigabyte/p34g-v2/thermal.h
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+// taken from Samsung / lumpy
+#ifndef P34V2_THERMAL_H
+#define P34V2_THERMAL_H
+
+/* Fan is OFF */
+#define FAN4_THRESHOLD_OFF 0
+#define FAN4_THRESHOLD_ON 0
+
+/* Fan is at LOW speed */
+#define FAN3_THRESHOLD_OFF 40
+#define FAN3_THRESHOLD_ON 44
+
+/* Fan is at MEDIUM speed */
+#define FAN2_THRESHOLD_OFF 44
+#define FAN2_THRESHOLD_ON 48
+
+/* Fan is at HIGH speed */
+#define FAN1_THRESHOLD_OFF 48
+#define FAN1_THRESHOLD_ON 54
+
+/* Fan is at FULL speed */
+#define FAN0_THRESHOLD_OFF 54
+#define FAN0_THRESHOLD_ON 78
+
+/* Temperature which OS will shutdown at */
+#define CRITICAL_TEMPERATURE 100
+
+/* Temperature which OS will throttle CPU */
+#define PASSIVE_TEMPERATURE 80
+
+/* Tj_max value for calculating PECI CPU temperature */
+#define MAX_TEMPERATURE 100
+
+#endif
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 28e3544..c1b3c50 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -962,8 +962,16 @@
{
spi_finalize_ops();

- if (acpi_is_wakeup_s3() || CONFIG(INTEL_CHIPSET_LOCKDOWN))
+ if (acpi_is_wakeup_s3() || CONFIG(INTEL_CHIPSET_LOCKDOWN)) {
outb(APM_CNT_FINALIZE, APM_CNT);
+ if (CONFIG(CONSOLE_SPI_FLASH)) {
+ /* Re-init SPI driver to handle locked BAR.
+ This prevents flashconsole from hanging.
+ If other code needs to use SPI during
+ ramstage, whitelist it here. */
+ spi_init();
+ }
+ }
}

static struct pci_operations pci_ops = {

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I5d83fbc4e402a9c0819947b8ea1ef2e480c3e5cb
Gerrit-Change-Number: 36072
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Maslowski <info@orangecms.org>
Gerrit-Reviewer: Daniel Maslowski <info@orangecms.org>
Gerrit-Reviewer: Martin Roth <martinroth@google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com>
Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org>
Gerrit-MessageType: newchange