Attention is currently required from: Jonathon Hall, Nicholas Sudsgaard.

Nico Huber uploaded patch set #2 to this change.

View Change

soc/intel/jasperlake: Drop redundant PcieRpEnable

The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infracture instead.

Thanks to Nicholas for doing all the mainboard legwork!

Change-Id: Iea7f616f6db579c06722369c08de7cf7261dece8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
---
M src/mainboard/google/dedede/variants/baseboard/devicetree.cb
M src/mainboard/google/dedede/variants/baseboard/ramstage.c
M src/mainboard/google/dedede/variants/boxy/overridetree.cb
M src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
M src/mainboard/google/dedede/variants/dexi/overridetree.cb
M src/mainboard/google/dedede/variants/dibbi/overridetree.cb
M src/mainboard/google/dedede/variants/dita/overridetree.cb
M src/mainboard/google/dedede/variants/sasuke/overridetree.cb
M src/mainboard/google/dedede/variants/sasukette/overridetree.cb
M src/mainboard/google/dedede/variants/storo/overridetree.cb
M src/mainboard/google/dedede/variants/taranza/overridetree.cb
M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
M src/mainboard/purism/librem_jsl/devicetree.cb
M src/soc/intel/jasperlake/Makefile.inc
M src/soc/intel/jasperlake/chip.c
M src/soc/intel/jasperlake/chip.h
A src/soc/intel/jasperlake/include/soc/pcie.h
A src/soc/intel/jasperlake/pcie_rp.c
M src/soc/intel/jasperlake/romstage/fsp_params.c
19 files changed, 38 insertions(+), 81 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/79919/2

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