Jonathan Zhang uploaded patch set #6 to this change.

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vendorcode/intel/fsp: update Cooperlake-SP header files

Update Cooperlake-SP (CPX-SP) FSP header files.

As CPX-SP FSP engineering is on-going (the processor Mass Production
is some time in this year). These header files will be adjusted when
changes are necessary with newer FSP release. This commit corresponds
to FSP release 1025293.

Also update soc/xeon_sp code file and Skylake-SP header file accordingly
to use FsptPort80RouteDisable instead of PcdPort80RouteDisable.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: I8bc6882e47de23d83ba0f521bb12a10dace523ce
---
M src/soc/intel/xeon_sp/bootblock.c
M src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FsptUpd.h
M src/vendorcode/intel/fsp/fsp2_1/cooperlake_sp/FspUpd.h
M src/vendorcode/intel/fsp/fsp2_1/cooperlake_sp/FspmUpd.h
M src/vendorcode/intel/fsp/fsp2_1/cooperlake_sp/FspsUpd.h
M src/vendorcode/intel/fsp/fsp2_1/cooperlake_sp/FsptUpd.h
A src/vendorcode/intel/fsp/fsp2_1/cooperlake_sp/gpio_fsp.h
A src/vendorcode/intel/fsp/fsp2_1/cooperlake_sp/hob_iiouds.h
A src/vendorcode/intel/fsp/fsp2_1/cooperlake_sp/hob_memmap.h
9 files changed, 1,384 insertions(+), 36 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/40034/6

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