Wonkyu Kim uploaded patch set #8 to this change.

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soc/intel/tigerlake: Configure L1Substates for PCH Root ports

Set value for PcieRpL1Substates according to devicetree.

Chip config parameter PcieRpL1Substates uses (UPD value + 1)
because UPD value of 0 for PcieRpL1Substates means disabled for FSP.
In order to ensure that mainboard setting does not disable L1 substates
incorrectly, chip config parameter values are offset by 1 with 0 meaning
use FSP UPD default.

get_l1_substate_control() ensures that the right UPD value is set in
fsp_params.

Chip config parameter values
0: Use FSP UPD default
1: Disable L1 substates
2: Use L1.1
3: Use L1.2 (FSP UPD default)

BUG=none
BRANCH=none
TEST=Boot up and check FSP log for PCIe config for this values

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I66743a29ad182bd49b501ae73b79270a9eb88450
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params_tgl.c
2 files changed, 32 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/39412/8

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