Patrick Rudolph has uploaded this change for review.
[TESTME]x4x/i82801jx/socket_LGA775: Add x86_64 support
Use correct datasize to compile on x86_64.
Change-Id: Ib4851932975e99e06ba5650c2359a835b46d702d
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
---
M src/arch/x86/walkcbfs.S
M src/cpu/intel/model_1067x/Kconfig
M src/cpu/intel/model_6fx/Kconfig
M src/cpu/intel/model_f3x/Kconfig
M src/cpu/intel/model_f4x/Kconfig
M src/cpu/intel/socket_LGA775/Kconfig
M src/cpu/x86/mp_init.c
M src/cpu/x86/smm/smm_module_handler.c
M src/drivers/net/atl1e.c
M src/northbridge/intel/x4x/dq_dqs.c
M src/northbridge/intel/x4x/northbridge.c
M src/northbridge/intel/x4x/raminit_ddr23.c
M src/northbridge/intel/x4x/rcven.c
M src/northbridge/intel/x4x/x4x.h
M src/southbridge/intel/common/spi.c
M src/southbridge/intel/i82801jx/hdaudio.c
M src/southbridge/intel/i82801jx/lpc.c
M src/southbridge/intel/i82801jx/sata.c
18 files changed, 63 insertions(+), 40 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/36779/1
diff --git a/src/arch/x86/walkcbfs.S b/src/arch/x86/walkcbfs.S
index ded6558..01382e4 100644
--- a/src/arch/x86/walkcbfs.S
+++ b/src/arch/x86/walkcbfs.S
@@ -33,6 +33,7 @@
.section .text
.global walkcbfs_asm
+.code32
/*
* input %esi: filename
diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig
index 564a428..93604d6 100644
--- a/src/cpu/intel/model_1067x/Kconfig
+++ b/src/cpu/intel/model_1067x/Kconfig
@@ -1,9 +1,14 @@
config CPU_INTEL_MODEL_1067X
bool
- select ARCH_BOOTBLOCK_X86_32
- select ARCH_VERSTAGE_X86_32
- select ARCH_ROMSTAGE_X86_32
- select ARCH_RAMSTAGE_X86_32
+ select ARCH_BOOTBLOCK_X86_32 if !ARCH_EXP_X86_64
+ select ARCH_VERSTAGE_X86_32 if !ARCH_EXP_X86_64
+ select ARCH_ROMSTAGE_X86_32 if !ARCH_EXP_X86_64
+ select ARCH_RAMSTAGE_X86_32 if !ARCH_EXP_X86_64
+ select ARCH_BOOTBLOCK_X86_64 if ARCH_EXP_X86_64
+ select ARCH_VERSTAGE_X86_64 if ARCH_EXP_X86_64
+ select ARCH_ROMSTAGE_X86_64 if ARCH_EXP_X86_64
+ select ARCH_RAMSTAGE_X86_64 if ARCH_EXP_X86_64
+
select SMP
select SSE2
select UDELAY_TSC
diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig
index cfd3e7c..8c86226 100644
--- a/src/cpu/intel/model_6fx/Kconfig
+++ b/src/cpu/intel/model_6fx/Kconfig
@@ -1,9 +1,14 @@
config CPU_INTEL_MODEL_6FX
bool
- select ARCH_BOOTBLOCK_X86_32
- select ARCH_VERSTAGE_X86_32
- select ARCH_ROMSTAGE_X86_32
- select ARCH_RAMSTAGE_X86_32
+ select ARCH_BOOTBLOCK_X86_32 if !ARCH_EXP_X86_64
+ select ARCH_VERSTAGE_X86_32 if !ARCH_EXP_X86_64
+ select ARCH_ROMSTAGE_X86_32 if !ARCH_EXP_X86_64
+ select ARCH_RAMSTAGE_X86_32 if !ARCH_EXP_X86_64
+
+ select ARCH_BOOTBLOCK_X86_64 if ARCH_EXP_X86_64
+ select ARCH_VERSTAGE_X86_64 if ARCH_EXP_X86_64
+ select ARCH_ROMSTAGE_X86_64 if ARCH_EXP_X86_64
+ select ARCH_RAMSTAGE_X86_64 if ARCH_EXP_X86_64
select SMP
select SSE2
select UDELAY_TSC
diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig
index 9a5e2a1..ae67337 100644
--- a/src/cpu/intel/model_f3x/Kconfig
+++ b/src/cpu/intel/model_f3x/Kconfig
@@ -1,9 +1,14 @@
config CPU_INTEL_MODEL_F3X
bool
- select ARCH_BOOTBLOCK_X86_32
- select ARCH_VERSTAGE_X86_32
- select ARCH_ROMSTAGE_X86_32
- select ARCH_RAMSTAGE_X86_32
+ select ARCH_BOOTBLOCK_X86_32 if !ARCH_EXP_X86_64
+ select ARCH_VERSTAGE_X86_32 if !ARCH_EXP_X86_64
+ select ARCH_ROMSTAGE_X86_32 if !ARCH_EXP_X86_64
+ select ARCH_RAMSTAGE_X86_32 if !ARCH_EXP_X86_64
+
+ select ARCH_BOOTBLOCK_X86_64 if ARCH_EXP_X86_64
+ select ARCH_VERSTAGE_X86_64 if ARCH_EXP_X86_64
+ select ARCH_ROMSTAGE_X86_64 if ARCH_EXP_X86_64
+ select ARCH_RAMSTAGE_X86_64 if ARCH_EXP_X86_64
select SMP
select SUPPORT_CPU_UCODE_IN_CBFS
select CPU_INTEL_COMMON
diff --git a/src/cpu/intel/model_f4x/Kconfig b/src/cpu/intel/model_f4x/Kconfig
index 4ef60b5..84c6863 100644
--- a/src/cpu/intel/model_f4x/Kconfig
+++ b/src/cpu/intel/model_f4x/Kconfig
@@ -1,8 +1,12 @@
config CPU_INTEL_MODEL_F4X
bool
- select ARCH_BOOTBLOCK_X86_32
- select ARCH_VERSTAGE_X86_32
- select ARCH_ROMSTAGE_X86_32
- select ARCH_RAMSTAGE_X86_32
+ select ARCH_BOOTBLOCK_X86_32 if !ARCH_EXP_X86_64
+ select ARCH_VERSTAGE_X86_32 if !ARCH_EXP_X86_64
+ select ARCH_ROMSTAGE_X86_32 if !ARCH_EXP_X86_64
+ select ARCH_RAMSTAGE_X86_32 if !ARCH_EXP_X86_64
+ select ARCH_BOOTBLOCK_X86_64 if ARCH_EXP_X86_64
+ select ARCH_VERSTAGE_X86_64 if ARCH_EXP_X86_64
+ select ARCH_ROMSTAGE_X86_64 if ARCH_EXP_X86_64
+ select ARCH_RAMSTAGE_X86_64 if ARCH_EXP_X86_64
select SMP
select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig
index 8b227bd..8f60d2c 100644
--- a/src/cpu/intel/socket_LGA775/Kconfig
+++ b/src/cpu/intel/socket_LGA775/Kconfig
@@ -3,6 +3,10 @@
if CPU_INTEL_SOCKET_LGA775
+config ARCH_EXP_X86_64
+ bool "Enable experimental 64bit support"
+ default n
+
config SOCKET_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_INTEL_MODEL_6FX
diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c
index 29ae3de..ea70453 100644
--- a/src/cpu/x86/mp_init.c
+++ b/src/cpu/x86/mp_init.c
@@ -122,7 +122,7 @@
/* The SIPI vector is loaded at the SMM_DEFAULT_BASE. The reason is at the
* memory range is already reserved so the OS cannot use it. That region is
* free to use for AP bringup before SMM is initialized. */
-static const uint32_t sipi_vector_location = SMM_DEFAULT_BASE;
+static const uintptr_t sipi_vector_location = SMM_DEFAULT_BASE;
static const int sipi_vector_location_size = SMM_DEFAULT_SIZE;
struct mp_flight_plan {
@@ -348,16 +348,16 @@
setup_default_sipi_vector_params(sp);
/* Setup MSR table. */
- sp->msr_table_ptr = (uint32_t)&mod_loc[module_size];
+ sp->msr_table_ptr = (uintptr_t)&mod_loc[module_size];
sp->msr_count = num_msrs;
/* Provide pointer to microcode patch. */
- sp->microcode_ptr = (uint32_t)mp_params->microcode_pointer;
+ sp->microcode_ptr = (uintptr_t)mp_params->microcode_pointer;
/* Pass on abiility to load microcode in parallel. */
if (mp_params->parallel_microcode_load)
sp->microcode_lock = 0;
else
sp->microcode_lock = ~0;
- sp->c_handler = (uint32_t)&ap_init;
+ sp->c_handler = (uintptr_t)&ap_init;
ap_count = &sp->ap_count;
atomic_set(ap_count, 0);
diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c
index bd4d48c..82ad37d 100644
--- a/src/cpu/x86/smm/smm_module_handler.c
+++ b/src/cpu/x86/smm/smm_module_handler.c
@@ -107,7 +107,7 @@
/* This function assumes all save states start at top of default
* SMRAM size space and are staggered down by save state size. */
- base = (void *)smm_runtime->smbase;
+ base = (void *)(uintptr_t)smm_runtime->smbase;
base += SMM_DEFAULT_SIZE;
base -= (cpu + 1) * smm_runtime->save_state_size;
diff --git a/src/drivers/net/atl1e.c b/src/drivers/net/atl1e.c
index 51470b0..d68ea0d 100644
--- a/src/drivers/net/atl1e.c
+++ b/src/drivers/net/atl1e.c
@@ -86,7 +86,7 @@
}
}
-static void program_mac_address(u32 mem_base)
+static void program_mac_address(uintptr_t mem_base)
{
u8 macstrbuf[MACLEN] = { 0 };
/* Default MAC Address of 90:e6:ba:24:f9:d2 */
@@ -110,7 +110,7 @@
printk(BIOS_DEBUG, "done\n");
}
-static int atl1e_eeprom_exist(u32 mem_base)
+static int atl1e_eeprom_exist(uintptr_t mem_base)
{
u32 value = read32((void *)mem_base + REG_SPI_FLASH_CTRL);
if (value & SPI_FLASH_CTRL_EN_VPD) {
diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c
index ed372b5..080262e 100644
--- a/src/northbridge/intel/x4x/dq_dqs.c
+++ b/src/northbridge/intel/x4x/dq_dqs.c
@@ -178,7 +178,7 @@
static u8 test_dq_aligned(const struct sysinfo *s,
const u8 channel)
{
- u32 address;
+ uintptr_t address;
int rank, lane;
u8 count, count1;
u8 data[8];
@@ -374,7 +374,7 @@
{
int i, rank, lane;
volatile u8 data[8];
- u32 address;
+ uintptr_t address;
u8 bytelane_error = 0;
FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, channel, rank) {
@@ -453,7 +453,8 @@
int do_read_training(struct sysinfo *s)
{
int loop, channel, i, lane, rank;
- u32 address, content;
+ uintptr_t address;
+ u32 content;
u8 dqs_lower[TOTAL_BYTELANES];
u8 dqs_upper[TOTAL_BYTELANES];
struct rt_dqs_setting dqs_setting[TOTAL_BYTELANES];
@@ -643,7 +644,7 @@
static void sample_dq(const struct sysinfo *s, u8 channel, u8 rank,
u8 high_found[8]) {
- u32 address = test_address(channel, rank);
+ uintptr_t address = test_address(channel, rank);
int samples, lane;
memset(high_found, 0, TOTAL_BYTELANES * sizeof(high_found[0]));
diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c
index 39f24d3..592a2e0 100644
--- a/src/northbridge/intel/x4x/northbridge.c
+++ b/src/northbridge/intel/x4x/northbridge.c
@@ -89,7 +89,7 @@
/* cbmem_top can be shifted downwards due to alignment.
Mark the region between cbmem_top and tomk as unusable */
- delta_cbmem = tomk - ((uint32_t)cbmem_top() >> 10);
+ delta_cbmem = tomk - ((uintptr_t)cbmem_top() >> 10);
tomk -= delta_cbmem;
uma_sizek += delta_cbmem;
diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c
index efdcbb6..31e94f4 100644
--- a/src/northbridge/intel/x4x/raminit_ddr23.c
+++ b/src/northbridge/intel/x4x/raminit_ddr23.c
@@ -1316,7 +1316,7 @@
void send_jedec_cmd(const struct sysinfo *s, u8 r, u8 ch, u8 cmd, u32 val)
{
- u32 addr = test_address(ch, r);
+ uintptr_t addr = test_address(ch, r);
u8 data8 = cmd;
u32 data32;
@@ -2160,7 +2160,7 @@
if (s->boot_path == BOOT_PATH_NORMAL) {
FOR_EACH_POPULATED_RANK(s->dimms, ch, r) {
for (bank = 0; bank < 4; bank++)
- read32((u32 *)(test_address(ch, r) | 0x800000 | (bank << 12)));
+ read32((u32 *)((uintptr_t)test_address(ch, r) | 0x800000 | (bank << 12)));
}
}
printk(BIOS_DEBUG, "Done dummy reads\n");
diff --git a/src/northbridge/intel/x4x/rcven.c b/src/northbridge/intel/x4x/rcven.c
index 36a6ebd..c41bb07 100644
--- a/src/northbridge/intel/x4x/rcven.c
+++ b/src/northbridge/intel/x4x/rcven.c
@@ -39,7 +39,7 @@
asm volatile("mfence":::);
}
-static u8 sampledqs(u32 addr, u8 lane, u8 channel)
+static u8 sampledqs(uintptr_t addr, u8 lane, u8 channel)
{
u32 sample_offset = 0x400 * channel + 0x561 + lane * 4;
diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h
index 76d94c6..4809ee7 100644
--- a/src/northbridge/intel/x4x/x4x.h
+++ b/src/northbridge/intel/x4x/x4x.h
@@ -84,9 +84,9 @@
* MCHBAR
*/
-#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x))))
-#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x))))
-#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x))))
+#define MCHBAR8(x) (*((volatile u8 *)((uintptr_t)DEFAULT_MCHBAR + (x))))
+#define MCHBAR16(x) (*((volatile u16 *)((uintptr_t)DEFAULT_MCHBAR + (x))))
+#define MCHBAR32(x) (*((volatile u32 *)((uintptr_t)DEFAULT_MCHBAR + (x))))
#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and))
#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or))
#define MCHBAR8_AND_OR(x, and, or) \
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index a84a0df..a9c8863 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -275,7 +275,7 @@
{
struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
uint8_t *rcrb; /* Root Complex Register Block */
- uint32_t rcba; /* Root Complex Base Address */
+ uintptr_t rcba; /* Root Complex Base Address */
uint8_t bios_cntl;
struct ich9_spi_regs *ich9_spi;
struct ich7_spi_regs *ich7_spi;
diff --git a/src/southbridge/intel/i82801jx/hdaudio.c b/src/southbridge/intel/i82801jx/hdaudio.c
index 0628c43..2273e6c 100644
--- a/src/southbridge/intel/i82801jx/hdaudio.c
+++ b/src/southbridge/intel/i82801jx/hdaudio.c
@@ -276,10 +276,8 @@
if (!res)
return;
- // NOTE this will break as soon as the Azalia get's a bar above
- // 4G. Is there anything we can do about it?
base = res2mmio(res, 0, 0);
- printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
+ printk(BIOS_DEBUG, "Azalia: base = %p\n", base);
codec_mask = codec_detect(base);
if (codec_mask) {
diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c
index a395069..412e97f 100644
--- a/src/southbridge/intel/i82801jx/lpc.c
+++ b/src/southbridge/intel/i82801jx/lpc.c
@@ -669,7 +669,7 @@
/* Add it to SSDT. */
acpigen_write_scope("\\");
- acpigen_write_name_dword("NVSA", (u32) gnvs);
+ acpigen_write_name_dword("NVSA", (u32)(uintptr_t) gnvs);
acpigen_pop_len();
}
}
diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c
index e6e08a3..70c5e69 100644
--- a/src/southbridge/intel/i82801jx/sata.c
+++ b/src/southbridge/intel/i82801jx/sata.c
@@ -37,7 +37,7 @@
u32 reg32;
/* Initialize AHCI memory-mapped space */
- u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
+ u8 *abar = (u8 *)(uintptr_t)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
printk(BIOS_DEBUG, "ABAR: %p\n", abar);
/* Set AHCI access mode.
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