Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/29660
Change subject: drivers/intel/fsp1_1: Add post console init functions for C bootblock ......................................................................
drivers/intel/fsp1_1: Add post console init functions for C bootblock
The console post init functions are not executed in C_ENVIRONMENT_BOOTBLOCK mode. Add car_XXXX_post_console_init functions to romstage_c_entry().
BUG=NA TEST=Portwell PQ7-M107
Change-Id: I12e613147e5203022cd453693a115fca002ce480 Signed-off-by: Frans Hendriks fhendriks@eltan.com --- M src/drivers/intel/fsp1_1/car.c 1 file changed, 10 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/29660/1
diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 4016ba1..4569454 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright 2015 Google Inc. + * Copyright 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -67,7 +68,10 @@ return cache_as_ram_stage_main(car_params->fih); }
-/* Entry point taken when romstage is called after a separate verstage. */ +/* + * Entry point taken when romstage is called after a separate verstage or + * when the C_ENVIRONMENT_BOOTBLOCK is enabled + */ asmlinkage void *romstage_c_entry(void) { /* Need to locate the current FSP_INFO_HEADER. The cache-as-ram @@ -77,6 +81,11 @@
console_init();
+ if (IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)) { + car_soc_post_console_init(); + car_mainboard_post_console_init(); + } + if (prog_locate(&fsp)) { fih = NULL; printk(BIOS_ERR, "Unable to locate %s\n", prog_name(&fsp));