[coreboot-gerrit] New patch to review for coreboot: ultra40m2: PCI SERR NMI crash workaround

[Jonathan A. Kollasch]

Jonathan A. Kollasch ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12305

-gerrit

commit 4b79850e3c9bba0a26df6365553d49502d70b786
Author: Jonathan A. Kollasch 
Date:   Tue Nov 3 10:31:17 2015 -0600

ultra40m2: PCI SERR NMI crash workaround

Change-Id: Ie399927bc7da07d84f3f0cf98aeb597b4916ad5e
    Signed-off-by: Jonathan A. Kollasch 
---
 src/device/pci_device.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index 5123229..20cf1ed 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -625,6 +625,11 @@ void pci_bus_enable_resources(struct device *dev)
    ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
    ctrl |= dev->link_list->bridge_ctrl;
    ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* Error check. */
+#if IS_ENABLED(CONFIG_BOARD_SUNW_ULTRA40M2)
+	if (strcmp(dev_path(dev), "PCI: 00:06.0") == 0) {
+		ctrl &= ~PCI_BRIDGE_CTL_SERR;
+	}
+#endif
    printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
    pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);